Patents by Inventor Seetharaman Ramachandran

Seetharaman Ramachandran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230369025
    Abstract: An edge ring centering system for a plasma processing system includes a processing chamber including a substrate support and R edge ring lift pins, where R is an integer greater than or equal to 3. An edge ring includes P grooves located on a bottom surface thereof, where P is an integer greater than or equal to R. A robot arm includes an end effector. A controller is configured to cause the optical sensor to sense a first position of the edge ring on the end effector; cause the robot arm to deliver the edge ring to a first center location on the edge ring lift pins; retrieve the edge ring from the edge ring lift pins; and cause the optical sensor to sense a second position of the edge ring on the end effector.
    Type: Application
    Filed: March 23, 2020
    Publication date: November 16, 2023
    Inventors: Hui Ling HAN, Seetharaman RAMACHANDRAN, Marc ESTOQUE
  • Publication number: 20230122167
    Abstract: A method for processing one or more substrates in a plasma processing chamber is provided. A plurality of cycles is provided, wherein each cycle comprises providing a pre-coat process, processing at least one substrate within the plasma processing chamber, and cleaning the plasma processing chamber. The providing the pre-coat process comprises one or more cycles of depositing a silicon containing pre-coat layer and depositing a carbon containing pre-coat layer.
    Type: Application
    Filed: March 10, 2021
    Publication date: April 20, 2023
    Inventors: Neil Marshall WILSON, Niklas ROSCHEWSKY, Seetharaman RAMACHANDRAN
  • Publication number: 20220285136
    Abstract: An edge ring system for a substrate processing system includes a top edge ring including an annular body having an inner diameter and an outer diameter. The outer diameter of the top edge ring is smaller than a horizontal opening of a substrate port of the substrate processing system. A first edge ring is arranged below the top edge ring including an annular body having an inner diameter and an outer diameter. The outer diameter of the first edge ring is larger than the substrate port of the substrate processing system. The inner diameter of the first edge ring is smaller than the inner diameter of the top edge ring.
    Type: Application
    Filed: July 30, 2020
    Publication date: September 8, 2022
    Inventors: Hui Ling HAN, Xinwei HUANG, Alexander Miller PATERSON, Saravanapriyan SRIRAMAN, Ann ERICKSON, Joanna WU, Seetharaman RAMACHANDRAN, Christopher KIMBALL, Aris PEREZ
  • Patent number: 9412670
    Abstract: A system and method of applying power to a target plasma chamber include, characterizing a no plasma performance slope of the target plasma chamber, applying a selected plasma recipe to a first wafer in the target chamber, the selected plasma recipe includes a selected power set point value and monitoring a recipe factor value on the RF electrode. A ratio of process efficiency is generated comparing the reference chamber and the target chamber, the generating using as inputs the no plasma performance slopes of the target chamber and the reference chamber and the monitored recipe factor value. An adjusted power set point value is calculated, the adjusted power set point configured to cause power delivered to a plasma formed in the target chamber to match power that would be delivered to a reference plasma formed in the reference chamber.
    Type: Grant
    Filed: May 23, 2013
    Date of Patent: August 9, 2016
    Assignee: Lam Research Corporation
    Inventors: Robert G. O'Neill, Arthur Sato, Eric Tonnis, Seetharaman Ramachandran, Shang-I Chou
  • Publication number: 20140349417
    Abstract: A system and method of applying power to a target plasma chamber include, characterizing a no plasma performance slope of the target plasma chamber, applying a selected plasma recipe to a first wafer in the target chamber, the selected plasma recipe includes a selected power set point value and monitoring a recipe factor value on the RF electrode. A ratio of process efficiency is generated comparing the reference chamber and the target chamber, the generating using as inputs the no plasma performance slopes of the target chamber and the reference chamber and the monitored recipe factor value. An adjusted power set point value is calculated, the adjusted power set point configured to cause power delivered to a plasma formed in the target chamber to match power that would be delivered to a reference plasma formed in the reference chamber.
    Type: Application
    Filed: May 23, 2013
    Publication date: November 27, 2014
    Applicant: Lam Research Corporation
    Inventors: Robert G. O'Neill, Arthur Sato, Eric Tonnis, Seetharaman Ramachandran, Shang-I Chou
  • Patent number: 8525139
    Abstract: A wafer is provided into an entrance load lock chamber. A vacuum is created in the entrance load lock chamber. The wafer is transported to a processing tool. The wafer is processed in a process chamber to provide a processed wafer, wherein the processing forms halogen residue. A degas step is provided in the process chamber after processing the wafer. The processed wafer is transferred into a degas chamber. The processed wafer is treated in the degas chamber with UV light and a flow of gas comprising at least one of ozone, oxygen, or H2O. The flow of gas is stopped. The UV light is stopped. The processed wafer is removed from the degas chamber.
    Type: Grant
    Filed: October 20, 2010
    Date of Patent: September 3, 2013
    Assignee: Lam Research Corporation
    Inventors: Harmeet Singh, Sanket Sant, Shang-I Chou, Vahid Vahedi, Raphael Casaes, Seetharaman Ramachandran
  • Publication number: 20110097902
    Abstract: A wafer is provided into an entrance load lock chamber. A vacuum is created in the entrance load lock chamber. The wafer is transported to a processing tool. The wafer is processed in a process chamber to provide a processed wafer, wherein the processing forms halogen residue. A degas step is provided in the process chamber after processing the wafer. The processed wafer is transferred into a degas chamber. The processed wafer is treated in the degas chamber with UV light and a flow of gas comprising at least one of ozone, oxygen, or H2O. The flow of gas is stopped. The UV light is stopped. The processed wafer is removed from the degas chamber.
    Type: Application
    Filed: October 20, 2010
    Publication date: April 28, 2011
    Applicant: LAM RESEARCH CORPORATION
    Inventors: Harmeet Singh, Sanket Sant, Shang-I Chou, Vahid Vahedi, Raphael Casaes, Seetharaman Ramachandran
  • Publication number: 20100119708
    Abstract: The present invention includes compositions, devices and methods for filling structures of high aspect ratio elements for growth amplification and device fabrication. A method includes a method of filling a structure comprising the steps of providing one or more structures, each structure having a plurality of high aspect ratio elements, wherein the aspect ratio is at least 5; and coating the plurality of high aspect ratio elements with at least one solidifying material produced by a form of chemical vapor deposition thereby forming a structured-film. Compositions of the present invention are solid formed structures that are less fragile, do not require such delicate handling to avoid serious degradation, are more stable, last longer, do not deform, and exhibit little stress as well as improved properties that include mechanical, chemical, electrical, biologic, and optical.
    Type: Application
    Filed: March 28, 2006
    Publication date: May 13, 2010
    Applicants: BOARD OF REGENTS THE UNIVERSITY OF TEXAS SYSTEM
    Inventors: Lawrence J. Overzet, Gil S. Lee, Anand Chandrashekar, Seetharaman Ramachandran, Jeong-Soo Lee, Slade H. Gardner