Abstract: The present technology includes semiconductor devices and methods with improved contact resistivity. Semiconductor devices include a substrate base, a contact including a silicide overlying at least a portion of the substrate in the one or more features, which has a contact length of less than 40 Angstroms. The methods for generating a reduced contact length silicide layer includes depositing a first metal, and performing at least one thermal anneal to generate a silicide having a reduced contact length.

Abstract: The present technology includes semiconductor devices and methods with improved contact resistivity. Semiconductor devices include a substrate base, a silicon oxide disposed on the base defining one or more features, a non-magnetic transition-metal doped contact silicide layer disposed on the substrate in the one or more features, and at least a first metal layer. The non-magnetic transition-metal doped contact silicide layer includes a non-magnetic transition-metal, a first metal, and a silicon containing compound, and includes greater than or about 8.0 E+13 per cm2 non-magnetic transition-metal atoms. The first metal layer includes the first metal and overlies the non-magnetic transition-metal doped contact silicide layer.

Abstract: This disclosure describes structures and methods for forming tapered vias between features in metal layers in semiconductor devices. Instead of straight vias that have 90° vertical sidewalls and a constant cross-sectional area throughout the height of the via, tapered vias may be formed that extend outward from one metal layer to a lower metal layer. The via may be allowed to expand in size in a direction parallel to the feature in the lower metal layer, while remaining a constant width so as not to expand beyond the footprint of the lower feature. This tapered shape results in a larger cross-sectional area at the interface between the via and the lower feature. This lowers the resistance of the via by increasing area for current flow, while also increasing the area of any liners which typically have higher resistances.

Abstract: The present technology includes semiconductor devices and methods with improved contact resistivity. Semiconductor devices include a substrate base, a silicon oxide disposed on the base defining one or more features, a bi-metallic silicide layer disposed on the substrate in the one or more features, and at least a first metal layer. The bi-metallic silicide layer includes a first metal, a second metal different than the first metal, and a silicon containing compound, and includes greater than or about 0.8 E+14 per cm?2 second metal atoms. The first metal layer includes the first metal and overlies the bi-metallic silicide layer.