Abstract: An image processing device includes: a controller configured to receive information for displaying at least a portion of an image, and in response thereto to generate a scale ratio K for scaling compressed image data corresponding to the image; a partial image decoder configured to receive the compressed image data and the scale ratio and in response thereto to decode and scale the compressed image data by the scale ratio K and to output a portion of the decoded and scaled image data, wherein the portion corresponds to an area of the image to be displayed on a display device; a frame buffer configured to store the portion of the decoded and scaled image data output by the partial image decoder; and a video processor configured to receive the data from the frame buffer and to further scale the data for display on the display device.

Abstract: A processor includes an emulator configured to receive an access command from a second memory controller, and a first memory controller configured to control an operation of a memory. The emulator is configured to determine whether the first memory controller is available to perform an operation corresponding to the access command, and transmit a wait signal to the second memory controller upon determining that the first memory controller is not available to perform the operation.

Abstract: An arbiter, a system, and a method for generating a pseudo-grant signal in response to a request and receiving target information in response to the pseudo-grant signal. The pseudo-grant signal reduces or eliminates waiting time.

Abstract: Video signal processing systems and methods for detecting horizontal synchronization signals within video signals. Digital filtering methods are implemented for processing analog video signals to determine time varying characteristics of video signals to detect the starting and ending positions of horizontal synchronization pulses in a video signal with increased accuracy. In addition, adaptive methods are implemented for dynamically determining various video signal parameters over time, such as blanking level BL, threshold value (slice) level and synchronization level SL using information extracted from digitally filtered video signals.

Abstract: A digital processing system and method for tracking a subcarrier included in a video signal are provided, where a phase comparator tracks the phase of a color burst signal based on predetermined supposed phases, Y/C separation and demodulation are carried out based on a compensation phase that is updated by a phase compensator in response to the tracked phase, and the Y/C separation and demodulation are performed based on a compensation frequency determined by a frequency compensator by checking short-term and long-term variations in the updated compensation phase.

Abstract: An image processing device includes: a controller configured to receive information for displaying at least a portion of an image, and in response thereto to generate a scale ratio K for scaling compressed image data corresponding to the image; a partial image decoder configured to receive the compressed image data and the scale ratio and in response thereto to decode and scale the compressed image data by the scale ratio K and to output a portion of the decoded and scaled image data, wherein the portion corresponds to an area of the image to be displayed on a display device; a frame buffer configured to store the portion of the decoded and scaled image data output by the partial image decoder; and a video processor configured to receive the data from the frame buffer and to further scale the data for display on the display device.

Abstract: A digital video signal processing apparatus and method for adaptive spatio-temporal Y/C separation in multiple directions. In the digital video signal processing apparatus, an adaptive three-dimensional band pass filter (3D BPF) performs Y/C separation using local comb filtering/1D band pass filtering when the edge direction is fixed vertically/horizontally according to spatio-temporal local characteristics of an image using spatio-temporal filters. When the edge direction is not fixed horizontally/vertically, the 3D BPF performs 2D band pass filtering in all directions. Thus, the 3D BPF continuously carries out comb filtering, 1D band pass filtering and 2D band pass filtering according to the spatio-temporal local characteristics of the image.

Abstract: Provided are an arbiter capable of improving memory access efficiency in a multi-bank memory, a memory access arbitration system including the arbiter, and an arbitration method thereof, where the arbiter detects requests that are not included in a busy bank, and allows the requests corresponding to a bank receiving the largest number of pending requests priorities; and write request information generated by masters is stored in a predetermined buffer to be output as additional master request information, and provides the corresponding master with an opportunity to generate new request information.

Abstract: Apparatus and method for dispatching a very long instruction word (VLIW) instruction having a variable length are provided. The apparatus for dispatching a VLIW instruction includes a packet buffer for storing at least one or more VLIW instructions, and a decoding unit configured to constitute a VLIW instruction to be currently executed among the VLIW instructions stored in the packet buffer and decode predetermined bits of each sub-instruction contained in the VLIW instruction. The apparatus dispatches a corresponding sub-instruction to an FU which corresponds to each sub-instruction, based on the results of decoding performed in the decoding unit, position information on the sub-instructions that are placed on the packet buffer, and position information on the sub-instructions that are placed in the current VLIW instruction. Sub-instructions can be effectively dispatched to corresponding FUs using simple decoding logic even in a case where the length of the VLIW instruction is not fixed.

Abstract: In the scanning conversion apparatus, a first converter converts input interlaced scan data into progressive scan data, and a second converter converting the progressive scan data output from the first converter to interlaced scan data.

Abstract: A digital video signal processing apparatus and method for adaptive spatio-temporal Y/C separation in multiple directions. In the digital video signal processing apparatus, an adaptive three-dimensional band pass filter (3D BPF) performs Y/C separation using local comb filtering/1D band pass filtering when the edge direction is fixed vertically/horizontally according to spatio-temporal local characteristics of an image using spatio-temporal filters. When the edge direction is not fixed horizontally/vertically, the 3D BPF performs 2D band pass filtering in all directions. Thus, the 3D BPF continuously carries out comb filtering, 1D band pass filtering and 2D band pass filtering according to the spatio-temporal local characteristics of the image.

Abstract: A digital data processor comprising a stack storage having a plurality of locations classified into two or more banks, and a stack pointer circuit pointing to one or more stack banks of the stack storage. The stack pointer circuit operates in response to decoding signals from an instruction decoder which decodes a current instruction to determine whether a one-word or a multi-word stack operation is desired.

Abstract: Video signal processing systems and methods for detecting horizontal synchronization signals within video signals. Digital filtering methods are implemented for processing analog video signals to determine time varying characteristics of video signals to detect the starting and ending positions of horizontal synchronization pulses in a video signal with increased accuracy. In addition, adaptive methods are implemented for dynamically determining various video signal parameters over time, such as blanking level BL, threshold value (slice) level and synchronization level SL using information extracted from digitally filtered video signals.

Abstract: An apparatus and method for controlling a variable bit rate in real time are provided, including an encoding unit for performing a predetermined image conversion on present video data to be encoded and for encoding the video data into a variable bit rate by quantizing the conversion result, and a variable bit rate controller for allocating an overall bit estimate of the video data to be stored in a system to each frame according to a variation in video recording time, for detecting the complexity of frames based on a difference between pixels of the encoded video data and for determining a quantization factor using the detected complexity.

Abstract: A digital processing system and method for tracking a subcarrier included in a video signal are provided, where a phase comparator tracks the phase of a color burst signal based on predetermined supposed phases, Y/C separation and demodulation are carried out based on a compensation phase that is updated by a phase compensator in response to the tracked phase, and the Y/C separation and demodulation are performed based on a compensation frequency determined by a frequency compensator by checking short-term and long-term variations in the updated compensation phase.

Abstract: A digital data processor comprising a stack storage having a plurality of locations classified into two or more banks, and a stack pointer circuit pointing to one or more stack banks of the stack storage. The stack pointer circuit operates in response to decoding signals from an instruction decoder which decodes a current instruction to determine whether a one-word or a multi-word stack operation is desired.

Abstract: A translation look-aside buffer (TLB) capable of reducing power consumption and improving performance of a memory is provided. The fully-associative TLB which converts a virtual address into a physical address, comprises a first TLB having a plurality of banks; a second TLB having a plurality of entries, each of which having one virtual page number and 2N physical page numbers, wherein N is a natural number; and a selection circuit for outputting an output signal of the first TLB to the second TLB in response to a selection signal, wherein each bank of the first TLB has a plurality of entries, each of which has one virtual page number and one physical page number. The size of a page indicated by a virtual page number of the first TLB is different from the size of a page indicated by a virtual page number of the second TLB.

Abstract: Provided are an arbiter capable of improving memory access efficiency in a multi-bank memory, a memory access arbitration system including the arbiter, and an arbitration method thereof, where the arbiter detects requests that are not included in a busy bank, and allows the requests corresponding to a bank receiving the largest number of pending requests priorities; and write request information generated by masters is stored in a predetermined buffer to be output as additional master request information, and provides the corresponding master with an opportunity to generate new request information.

Abstract: An apparatus and method of controlling a digital video (MPEG) player for reverse-play. The MPEG player is comprised of an I-frame buffer for storing I-pictures encoded from P-pictures by a video decoder, a B-frame buffer for storing B-pictures, and an I-frame encoder for decoding a P-picture into an I-picture. In the MPEG player, a picture group being played at present is decoded for reverse play and a previous picture group is decoded for preparation of the reverse-play. Reverse-play in soft 1-times (×1) by means of a frame memory of small capacity is achieved irrespective of the picture number and classes in picture groups.

Abstract: A semiconductor device having a main processor and a coprocessor for data processing is disclosed, the device comprising a main program memory for storing main processor instructions and a first portion of coprocessor instructions, a coprocessor program memory for storing a second portion of coprocessor instructions, and a predecoder for predecoding at least one bit of each instruction fetched from the main program memory and for generating an active coprocessor control signal upon predecoding a coprocessor type instruction, wherein the second portion of coprocessor instructions are fetched directly from the coprocessor program memory and the first portion and the second portion of coprocessor instructions are processed by the coprocessor upon receipt of the active coprocessor control signal.