Patents by Inventor SEI JOON KIM

SEI JOON KIM has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • ANALOG IN-SENSOR COMPUTING DEVICE AND ELECTRONIC DEVICE INCLUDING SAME
    Publication number: 20250013856
    Abstract: A convolutional neural network (CNN)-based analog in-sensor computing device may include a convolution layer including one or more convolution blocks configured to be used a predetermined number of times or more and perform a convolution operation, and an memory configured to temporarily store an output of the convolution layer and provide the stored analog output to a subsequent convolution layer.
    Type: Application
    Filed: April 19, 2024
    Publication date: January 9, 2025
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Min Young MUN, Seok Ju YUN, Sei Joon KIM, Sang Joon KIM
  • Semiconductor system including heterogeneous memory module
    Patent number: 10509744
    Abstract: A semiconductor system includes a CPU connected to a heterogeneous memory module via a system bus. The heterogeneous memory module includes; a volatile memory module, a nonvolatile memory module, an internal bus separate from the system bus and connecting the volatile memory module and the nonvolatile memory module, and a swap manager configured to control execution of a swap operation transferring target data between the volatile memory module and nonvolatile memory module using the internal bus and without using of the system bus.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: December 17, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeong Ho Lee, Sung Roh Yoon, Eui Young Chung, Jin Woo Kim, Young Jin Cho, Myeong Jin Kim, Sei Joon Kim, Jeong Bin Kim, Hyeok Jun Choe
  • SEMICONDUCTOR SYSTEM INCLUDING HETEROGENEOUS MEMORY MODULE
    Publication number: 20180189206
    Abstract: A semiconductor system includes a CPU connected to a heterogeneous memory module via a system bus. The heterogeneous memory module includes; a volatile memory module, a nonvolatile memory module, an internal bus separate from the system bus and connecting the volatile memory module and the nonvolatile memory module, and a swap manager configured to control execution of a swap operation transferring target data between the volatile memory module and nonvolatile memory module using the internal bus and without using of the system bus.
    Type: Application
    Filed: December 15, 2017
    Publication date: July 5, 2018
    Applicants: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION, INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: JEONG HO LEE, SUNG ROH YOON, EUI YOUNG CHUNG, JIN WOO KIM, YOUNG JIN CHO, MYEONG JIN KIM, SEI JOON KIM, JEONG BIN KIM, HYEOK JUN CHOE