Patents by Inventor Sei SAITOU

Sei SAITOU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10607978
    Abstract: A semiconductor device, including a first semiconductor chip including a first substrate having a semiconductor larger in bandgap than silicon, the first semiconductor chip being formed with a first FET including a first gate electrode, a first source, and a first drain, a second semiconductor chip including a second substrate having a semiconductor larger in bandgap than silicon, the second semiconductor chip being formed with a second FET having a second gate electrode, a second source, and a second drain, and a third semiconductor chip including a third substrate having silicon, the third semiconductor chip being formed with a MOSFET including a third gate electrode, a third source, and a third drain. The first semiconductor chip and the second semiconductor chip are mounted over a first chip mounting section, and the third semiconductor chip is mounted over a second chip mounting section.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: March 31, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Satoru Akiyama, Hiroyoshi Kobayashi, Hisao Inomata, Sei Saitou
  • Publication number: 20180166430
    Abstract: A semiconductor device, including a first semiconductor chip including a first substrate having a semiconductor larger in bandgap than silicon, the first semiconductor chip being formed with a first FET including a first gate electrode, a first source, and a first drain, a second semiconductor chip including a second substrate having a semiconductor larger in bandgap than silicon, the second semiconductor chip being formed with a second FET having a second gate electrode, a second source, and a second drain, and a third semiconductor chip including a third substrate having silicon, the third semiconductor chip being formed with a MOSFET including a third gate electrode, a third source, and a third drain. The first semiconductor chip and the second semiconductor chip are mounted over a first chip mounting section, and the third semiconductor chip is mounted over a second chip mounting section.
    Type: Application
    Filed: February 12, 2018
    Publication date: June 14, 2018
    Inventors: Satoru AKIYAMA, Hiroyoshi KOBAYASHI, Hisao INOMATA, Sei SAITOU
  • Patent number: 9960153
    Abstract: The manufacturing yield of a semiconductor device is improved. There is provided a semiconductor device of a cascode coupling system, which is equipped with a plurality of normally-on junction FETs using as a material, a substance larger in bandgap than silicon, and a normally-off MOSFET using silicon as a material. At this time, the semiconductor chip has a plurality of junction FET semiconductor chips (semiconductor chip CHP0 and semiconductor chip CHP1) formed with the junction FETs in a divided fashion, and a MOSFET semiconductor chip (semiconductor chip CHP2) formed with the MOSFET.
    Type: Grant
    Filed: June 8, 2015
    Date of Patent: May 1, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Satoru Akiyama, Hiroyoshi Kobayashi, Hisao Inomata, Sei Saitou
  • Patent number: 9917078
    Abstract: The manufacturing yield of a semiconductor device is improved. There is provided a semiconductor device of a cascode coupling system, which is equipped with a plurality of normally-on junction FETs using as a material, a substance larger in bandgap than silicon, and a normally-off MOSFET using silicon as a material. At this time, the semiconductor chip has a plurality of junction FET semiconductor chips (semiconductor chip CHP0 and semiconductor chip CHP1) formed with the junction FETs in a divided fashion, and a MOSFET semiconductor chip (semiconductor chip CHP2) formed with the MOSFET.
    Type: Grant
    Filed: June 8, 2015
    Date of Patent: March 13, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Satoru Akiyama, Hiroyoshi Kobayashi, Hisao Inomata, Sei Saitou
  • Publication number: 20160211246
    Abstract: The manufacturing yield of a semiconductor device is improved. There is provided a semiconductor device of a cascode coupling system, which is equipped with a plurality of normally-on junction FETs using as a material, a substance larger in bandgap than silicon, and a normally-off MOSFET using silicon as a material. At this time, the semiconductor chip has a plurality of junction FET semiconductor chips (semiconductor chip CHP0 and semiconductor chip CHP1) formed with the junction FETs in a divided fashion, and a MOSFET semiconductor chip (semiconductor chip CHP2) formed with the MOSFET.
    Type: Application
    Filed: June 8, 2015
    Publication date: July 21, 2016
    Inventors: Satoru AKIYAMA, Hiroyoshi KOBAYASHI, Hisao INOMATA, Sei SAITOU