Patents by Inventor Seiei Ohkoshi

Seiei Ohkoshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4346472
    Abstract: A code converting circuit of simple construction composed of an exclusive OR circuit and a flip-flop circuit is provided on each of transmitting and receiving sides of a digital data transmission system according to a differential phase shift keying system, to convert two consecutive errors on adjacent bits peculiar to the differential phase shift keying system into only an error on a single bit. As a result, it is not required to employ a code having an excellent error-correcting capacity in the digital data transmission system, and thus a high transmission efficiency is attained by the use of a code which is relatively deficient in error correcting capacity.
    Type: Grant
    Filed: August 7, 1980
    Date of Patent: August 24, 1982
    Assignees: Hitachi, Ltd., Nippon Telegraph & Telephone Public Corporation
    Inventors: Seiei Ohkoshi, Isao Ishikawa, Teiji Okamoto, Nobuo Tsukamoto
  • Patent number: 4292476
    Abstract: In a key telephone system including an electronic speech channel switching network and an electronic key telephone set selectively connected to central office lines by the speech channel switching network, the speech channel switching network is constituted by a pair of incoming lines connected to a pair of central office lines and a plurality of pairs of outgoing lines connected to the key telephone set. The incoming and outgoing lines are arranged in a matrix, and a plurality of controllable unidirectional switching elements are disposed respectively at four cross-points between the incoming and outgoing lines. Each switching element is connected oppositely with respect to one incoming line and to one outgoing line which comprise a pair.
    Type: Grant
    Filed: October 11, 1979
    Date of Patent: September 29, 1981
    Assignee: Nippon Telegraph and Telephone Public Corporation
    Inventors: Kazuyuki Yamamoto, Seiei Ohkoshi
  • Patent number: 4288862
    Abstract: A memory circuit comprising a memory cell for storing information, constituted of semiconductor circuit elements and the associated circuit elements, and a control input section provided on the input side of the memory cell for controlling the memory cell, constituted of transistor means and current control means, wherein one of ON and OFF states is selected and also held in accordance with more than two logic input signals supplied to the control input section and no power is consumed to hold the OFF state.
    Type: Grant
    Filed: December 19, 1978
    Date of Patent: September 8, 1981
    Assignees: Nippon Telegraph and Telephone Public Corp., Hitachi, Ltd.
    Inventors: Ichiro Ohhinata, Seiei Ohkoshi, Hideo Suzuki