Patents by Inventor Seigi ISHIJI

Seigi ISHIJI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11444557
    Abstract: A gate drive semiconductor device includes: external terminals to which PWM control signals are supplied; external terminals outputting a drive signal for driving a three-phase BLDC motor; external terminals to which the counter electromotive voltage generated by driving the three-phase BLDC motor is supplied; a zero-cross determination unit generating an interrupt signal indicating timing at which the counter electromotive voltage intersects with a midpoint potential of the three-phase BLDC motor based on the PWM control signal and the counter electromotive voltage; and an external terminal outputting the interrupt signal.
    Type: Grant
    Filed: January 13, 2021
    Date of Patent: September 13, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Seigi Ishiji, Minoru Kurosawa
  • Publication number: 20210273589
    Abstract: A gate drive semiconductor device includes: external terminals to which PWM control signals are supplied; external terminals outputting a drive signal for driving a three-phase BLDC motor; external terminals to which the counter electromotive voltage generated by driving the three-phase BLDC motor is supplied; a zero-cross determination unit generating an interrupt signal indicating timing at which the counter electromotive voltage intersects with a midpoint potential of the three-phase BLDC motor based on the PWM control signal and the counter electromotive voltage; and an external terminal outputting the interrupt signal.
    Type: Application
    Filed: January 13, 2021
    Publication date: September 2, 2021
    Inventors: Seigi ISHIJI, Minoru KUROSAWA
  • Patent number: 10348220
    Abstract: A PWM modulation circuit controls low-side transistors of three phases to all be in an ON state when a brake current flows; controls, in a period in which a brake current flows in a first direction in one phase, a transistor for sensing in that one phase to be in an ON state; and controls, in a period in which a brake current flows in the first direction in two phases, transistors for three phases to be in an OFF state. When the brake current is to flow, sense-phase control circuits for the three phases control a transistor for sensing, in a phase in which the brake current flows in a sink direction, to be into an ON state, and controls the transistor for sensing in a phase in which the brake current flows in an opposite direction, to be into an OFF state.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: July 9, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Minoru Kurosawa, Seigi Ishiji
  • Publication number: 20190006964
    Abstract: A PWM modulation circuit controls low-side transistors of three phases (u, v, and w) all to be into an ON state, when a brake current flows, controls, in a period in which a brake current flows in one phase, a transistor for sensing (u, v, and w) of this one phase to be into an ON state, and controls, in a period of two phases, the transistor for sensing (u, v, and w) of three phases to be into an OFF state. When the brake current is to flow, sense-phase control circuits of three phases controls a transistor for sensing (u, v, and w), in a phase in which the brake current is in a sink direction, to be into an ON state, and controls the transistor for sensing (u, v, and w) in a phase in which it is in an opposite direction, to be into an OFF state.
    Type: Application
    Filed: June 11, 2018
    Publication date: January 3, 2019
    Applicant: Renesas Electronics Corporation
    Inventors: Minoru KUROSAWA, Seigi ISHIJI
  • Patent number: 10056107
    Abstract: A control device is provided which can perform a retraction operation of a head included in a disk storage device with lower power consumption. The control device of the disk storage device includes a control unit that controls a motor and retracts the head from over a disk to a ramp mechanism when power supply is shut down, an acquisition unit that acquires information related to a moving distance of the head that retracts to the ramp mechanism, and a calculation unit that calculates the moving distance of the head based on the information acquired by the acquisition unit. The control unit switches an operation of the motor from a first retract operation to a second retract operation when determining that the head reaches a first position after passing through an inclined surface of the ramp mechanism based on the moving distance calculated by the calculation unit.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: August 21, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Minoru Kurosawa, Kichiya Itagaki, Seigi Ishiji
  • Publication number: 20180096704
    Abstract: A control device is provided which can perform a retraction operation of a head included in a disk storage device with lower power consumption. The control device of the disk storage device includes a control unit that controls a motor and retracts the head from over a disk to a ramp mechanism when power supply is shut down, an acquisition unit that acquires information related to a moving distance of the head that retracts to the ramp mechanism, and a calculation unit that calculates the moving distance of the head based on the information acquired by the acquisition unit. The control unit switches an operation of the motor from a first retract operation to a second retract operation when determining that the head reaches a first position after passing through an inclined surface of the ramp mechanism based on the moving distance calculated by the calculation unit.
    Type: Application
    Filed: September 27, 2017
    Publication date: April 5, 2018
    Applicant: Renesas Electronics Corporation
    Inventors: Minoru KUROSAWA, Kichiya ITAGAKI, Seigi ISHIJI
  • Patent number: 9503011
    Abstract: The present invention is intended to reduce noise and vibration of a motor. A first duty correction circuit generates a first corrected duty instruction value which changes with an increment same as an increment of a duty instruction value and in which an offset value as a constant is reflected. A second duty correction circuit generates a second corrected duty instruction value which changes with an increment different from an increment of the duty instruction value. A selector outputs, as the corrected duty instruction value, either one of the first corrected duty instruction value and the second corrected duty instruction value in accordance with a magnitude relation between the duty instruction value and a duty reference value.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: November 22, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Minoru Kurosawa, Kichiya Itagaki, Seigi Ishiji
  • Publication number: 20160241177
    Abstract: The present invention is intended to reduce noise and vibration of a motor. A first duty correction circuit generates a first corrected duty instruction value which changes with an increment same as an increment of a duty instruction value and in which an offset value as a constant is reflected. A second duty correction circuit generates a second corrected duty instruction value which changes with an increment different from an increment of the duty instruction value. A selector outputs, as the corrected duty instruction value, either one of the first corrected duty instruction value and the second corrected duty instruction value in accordance with a magnitude relation between the duty instruction value and a duty reference value.
    Type: Application
    Filed: November 19, 2015
    Publication date: August 18, 2016
    Inventors: Minoru KUROSAWA, Kichiya ITAGAKI, Seigi ISHIJI