Patents by Inventor Seigo Abe
Seigo Abe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10724598Abstract: An active vibration isolator including a movable stage provides good vibration isolation performance. An active vibration isolator includes: a stage moving under thrust to position a mounted object; a vibration isolation table supporting the stage; a servo valve imparting, to the vibration isolation table, a control force that reduces vibrations of the vibration isolation table; a position/thrust obtaining unit obtaining a position of the stage on a movement track and the thrust actually applied to the stage with movement of the stage; and a vibration control FF control unit performing feed-forward control of the servo valve, based on what is obtained by the position/thrust obtaining unit, to allow the servo valve to generate a control force commensurate with vibrations of the vibration isolation table caused by the movement of the stage.Type: GrantFiled: July 26, 2018Date of Patent: July 28, 2020Assignee: KURASHIKI KAKO CO., LTD.Inventors: Ichiro Kishimoto, Seigo Abe, Rina Hoshida, Min Li, Shingo Takahashi
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Publication number: 20190032747Abstract: An active vibration isolator including a movable stage provides good vibration isolation performance. An active vibration isolator includes: a stage moving under thrust to position a mounted object; a vibration isolation table supporting the stage; a servo valve imparting, to the vibration isolation table, a control force that reduces vibrations of the vibration isolation table; a position/thrust obtaining unit obtaining a position of the stage on a movement track and the thrust actually applied to the stage with movement of the stage; and a vibration control FF control unit performing feed-forward control of the servo valve, based on what is obtained by the position/thrust obtaining unit, to allow the servo valve to generate a control force commensurate with vibrations of the vibration isolation table caused by the movement of the stage.Type: ApplicationFiled: July 26, 2018Publication date: January 31, 2019Applicant: KURASHIKI KAKO CO., LTD.Inventors: Ichiro KISHIMOTO, Seigo ABE, Rina HOSHIDA, Min LI, Shingo TAKAHASHI
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Patent number: 7224003Abstract: The present invention provides a solid-state image pickup apparatus which is able to easily discharge signal charges in a signal accumulating section and which is free from reduction in the dynamic range of the element, thermal noise in a dark state, an image-lag and so forth even if the pixel size of the MOS solid-state image pickup apparatus is reduced, the voltage of a reading gate is lowered and the concentration in the well is raised. The solid-state image pickup apparatus according to the present invention incorporates a p-type silicon substrate having a surface on which a p+ diffusion layer for constituting a photoelectric conversion region and a drain of a reading MOS field effect transistor are formed. A signal accumulating section formed by an n-type diffusion layer is formed below the p+ diffusion layer. A gate electrode of the MOS field effect transistor is, on the surface of the substrate, formed between the p+ diffusion layer and the drain.Type: GrantFiled: March 24, 2006Date of Patent: May 29, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Nobuo Nakamura, Hisanori Ihara, Ikuko Inoue, Hidenori Shibata, Akiko Nomachi, Yoshiyuki Shioyama, Hidetoshi Nozaki, Masako Hori, Akira Makabe, Hiroshi Naruse, Hideki Inokuma, Seigo Abe, Hirofumi Yamashita, Tetsuya Yamaguchi
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Publication number: 20060163684Abstract: The present invention provides a solid-state image pickup apparatus which is able to easily discharge signal charges in a signal accumulating section and which is free from reduction in the dynamic range of the element, thermal noise in a dark state, an image-lag and so forth even if the pixel size of the MOS solid-state image pickup apparatus is reduced, the voltage of a reading gate is lowered and the concentration in the well is raised. The solid-state image pickup apparatus according to the present invention incorporates a p-type silicon substrate having a surface on which a p+ diffusion layer for constituting a photoelectric conversion region and a drain of a reading MOS field effect transistor are formed. A signal accumulating section formed by an n-type diffusion layer is formed below the p+ diffusion layer. A gate electrode of the MOS field effect transistor is, on the surface of the substrate, formed between the p+ diffusion layer and the drain.Type: ApplicationFiled: March 24, 2006Publication date: July 27, 2006Inventors: Nobuo Nakamura, Hisanori Ihara, Ikuko Inoue, Hidenori Shibata, Akiko Nomachi, Yoshiyuki Shioyama, Hidetoshi Nozaki, Masako Hori, Akira Makabe, Hiroshi Naruse, Hideki Inokuma, Seigo Abe, Hirofumi Yamashita, Tetsuya Yamaguchi
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Patent number: 7042061Abstract: The present invention provides a solid-state image pickup apparatus which is able to easily discharge signal charges in a signal accumulating section and which is free from reduction in the dynamic range of the element, thermal noise in a dark state, an image-lag and so forth even if the pixel size of the MOS solid-state image pickup apparatus is reduced, the voltage of a reading gate is lowered and the concentration in the well is raised. The solid-state image pickup apparatus according to the present invention incorporates a p-type silicon substrate having a surface on which a p+ diffusion layer for constituting a photoelectric conversion region and a drain of a reading MOS field effect transistor are formed. A signal accumulating section formed by an n-type diffusion layer is formed below the p+ diffusion layer. A gate electrode of the MOS field effect transistor is, on the surface of the substrate, formed between the p+ diffusion layer and the drain.Type: GrantFiled: December 5, 2003Date of Patent: May 9, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Nobuo Nakamura, Hisanori Ihara, Ikuko Inoue, Hidenori Shibata, Akiko Nomachi, Yoshiyuki Shioyama, Hidetoshi Nozaki, Masako Hori, Akira Makabe, Hiroshi Naruse, Hideki Inokuma, Seigo Abe, Hirofumi Yamashita, Tetsuya Yamaguchi
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Publication number: 20040108502Abstract: The present invention provides a solid-state image pickup apparatus which is able to easily discharge signal charges in a signal accumulating section and which is free from reduction in the dynamic range of the element, thermal noise in a dark state, an image-lag and so forth even if the pixel size of the MOS solid-state image pickup apparatus is reduced, the voltage of a reading gate is lowered and the concentration in the well is raised. The solid-state image pickup apparatus according to the present invention incorporates a p-type silicon substrate having a surface on which a p+ diffusion layer for constituting a photoelectric conversion region and a drain of a reading MOS field effect transistor are formed. A signal accumulating section formed by an n-type diffusion layer is formed below the p+ diffusion layer. A gate electrode of the MOS field effect transistor is, on the surface of the substrate, formed between the p+ diffusion layer and the drain.Type: ApplicationFiled: December 5, 2003Publication date: June 10, 2004Inventors: Nobuo Nakamura, Hisanori Ihara, Ikuko Inoue, Hidenori Shibata, Akiko Nomachi, Yoshiyuki Shioyama, Hidetoshi Nozaki, Masako Hori, Akira Makabe, Hiroshi Naruse, Hideki Inokuma, Seigo Abe, Hirofumi Yamashita, Tetsuya Yamaguchi
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Patent number: 6690423Abstract: The present invention provides a solid-state image pickup apparatus which is able to easily discharge signal charges in a signal accumulating section and which is free from reduction in the dynamic range of the element, thermal noise in a dark state, an image-lag and so forth even if the pixel size of the MOS solid-state image pickup apparatus is reduced, the voltage of a reading gate is lowered and the concentration in the well is raised. The solid-state image pickup apparatus according to the present invention incorporates a p-type silicon substrate having a surface on which a p+ diffusion layer for constituting a photoelectric conversion region and a drain of a reading MOS field effect transistor are formed. A signal accumulating section formed by an n-type diffusion layer is formed below the p+ diffusion layer. A gate electrode of the MOS field effect transistor is, on the surface of the substrate, formed between the p+ diffusion layer and the drain.Type: GrantFiled: March 19, 1999Date of Patent: February 10, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Nobuo Nakamura, Hisanori Ihara, Ikuko Inoue, Hidenori Shibata, Akiko Nomachi, Yoshiyuki Shioyama, Hidetoshi Nozaki, Masako Hori, Akira Makabe, Hiroshi Naruse, Hideki Inokuma, Seigo Abe, Hirofumi Yamashita, Tetsuya Yamaguchi