Abstract: A memory card controller is provided with a clock start/end control unit that suspends supply of a clock signal to the memory card when a data amount transferred from the memory card as a result of the transfer operation reaches a data amount specified by an nth command received from the host device. The memory card controller resumes supply of the clock signal to the memory card if a subsequent command received with supply of the clock signal to the SD card in a suspended state specifies an address consecutive to an end address of data transfer requested by the nth command as a start address.

Abstract: A memory card controller for controlling data transfer between a host device that requests data transfer by issuing a command specifying a data amount and a memory card that executes a transfer operation from receipt of a transfer start instruction until receipt of a transfer end instruction. The memory card controller is provided with a clock start/end control unit 10 that suspends supply of a clock signal to the memory card when a data amount transferred from the memory card as a result of the transfer operation reaches a data amount specified by an nth command received from the host device, and resumes supply of the clock signal to the memory card if a subsequent command received with supply of the clock signal to the SD card in a suspended state specifies an address consecutive to an end address of data transfer requested by the nth command as a start address.

Abstract: The receiver and transmitter/receiver in accordance with the present invention comprises a common input terminal for inputting digital data including uncompressed video data or compressed video data, a receiving circuit for carrying out serial-parallel conversion processing for the digital data from the above-mentioned common input terminal and for carrying output, an SDI decoder and an SDTI decoder for inputting data from the above-mentioned receiving circuit and for taking out the digital data including the uncompressed video data and compressed video data, respectively, a distinguishing circuit for distinguishing the transmission format of the input digital data and the presence or absence of the compression of the video data, and a selection switch for selecting data from the SDI decoder or the SDTI decoder on the basis of the result of the distinguishing of the distinguishing circuit.