Patents by Inventor Seiichi Aritomo

Seiichi Aritomo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040174747
    Abstract: The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite oepration, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.
    Type: Application
    Filed: March 19, 2004
    Publication date: September 9, 2004
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tomoharu Tanaka, Masaki Momodomi, Hideo Kato, Hiroto Nakai, Yoshiyuki Tanaka, Riichiro Shirota, Seiichi Aritomo, Yasuo Itoh, Yoshihisa Iwata, Hiroshi Nakamura, Hideko Odaira, Yutaka Okamoto, Masamichi Asano, Kaoru Tokushige