Abstract: The potential of a source terminal of a transistor is fixed; a load is connected to a drain terminal of the transistor; and an input signal is received by a gate terminal of the transistor. A series circuit including an inductor and a capacitor connected in series is provided between a connection point of the drain terminal of the transistor and the load and an output terminal of a high-frequency circuit. A band-pass filter having a prescribed characteristic is configured by an output equivalent circuit expressing an output impedance of the transistor, the load, and the series circuit.

Abstract: A cascade-connected transistor includes a common-source transistor which receives an input signal, and a common-gate transistor which is connected to a drain terminal of the common-source transistor and outputs an output signal. A band-pass filter receives the output signal of the cascade-connected transistors. An adjustment circuit is interposed between the drain terminal and the gate terminal of the common-gate transistor, and adjusts the output impedance of the cascade-connected transistor.

Abstract: The potential of a source terminal of a transistor is fixed; a load is connected to a drain terminal of the transistor; and an input signal is received by a gate terminal of the transistor. A series circuit including an inductor and a capacitor connected in series is provided between a connection point of the drain terminal of the transistor and the load and an output terminal of a high-frequency circuit. A band-pass filter having a prescribed characteristic is configured by an output equivalent circuit expressing an output impedance of the transistor, the load, and the series circuit.

Abstract: A mixer circuit receives a local signal and an input signal so as to output a high-frequency signal generated based on the received signals. An output buffer receives the high-frequency signal. A band-pass filter having predetermined characteristics is formed by using the parameters of passive elements included in an output equivalent circuit as viewed from an output terminal of the mixer circuit and the parameters of passive elements included in an input equivalent circuit as viewed from an input terminal of the output buffer circuit.

Abstract: A cascode-connected transistor includes a common-source transistor which receives an input signal, and a common-gate transistor which is connected to a drain terminal of the common-source transistor and outputs an output signal. A band-pass filter receives the output signal of the cascode-connected transistors. An adjustment circuit is interposed between the drain terminal and the gate terminal of the common-gate transistor, and adjusts the output impedance of the cascode-connected transistor.

Abstract: An embodiment of the present invention relates to impedance matching applied to a radio apparatus having an antenna. The antenna transmits and receives a signal of a predetermined frequency band. A high-frequency signal processing unit performs a signal processing on the signal transmitted from and received by the antenna. The signal path connects the antenna with the high-frequency processing unit. The signal path is structured in a manner such that, at one point between the antenna and the high-frequency signal processing unit, the signal path is branched out to a plurality of branched line paths that each include at least an inductance component and a capacitance component and, at another point between them, the respective branched-out branched line paths are gathered. By adjusting the number of a plurality of branched line paths, the impedance is matched in the predetermined frequency band.

Abstract: An analog-to-digital conversion apparatus which has a variable resolution and allows a reduction in power consumption. This apparatus comprises an analog-to-digital converter (ADC) of parallel type, a controller, and an interpolation circuit. The analog-to-digital converter has a plurality of comparators connected in parallel, each for comparing potentials of an analog input signal and a reference signal. The controller generates a control signal for controlling the resolution of the analog-to-digital converter. Specifically, the controller controls the number of comparators (CMP) to operate by means of the control signal, thereby determining the resolution. The interpolation circuit interpolates the output data of the comparators that are disabled depending on the resolution. The controller avoids simultaneous operation of two adjoining comparators when the analog-to-digital converter is operated at a resolution lower than its maximum resolution.

Abstract: A general purpose of the present invention is to stabilize a filter circuit to desired characteristics without increasing its circuit scale. An active filter unit includes a current control unit, a first gm-C filter unit, and a subsequent circuit. Using a signal output from a central control unit as an input, the current control unit outputs adjustment currents for adjusting gm values, corresponding to respective transconductance amplifiers, to the first gm-C filter unit. The subsequent circuit includes a load capacitance which is composed of an active element such as a transconductance amplifier. The first gm-C filter unit includes the plurality of transconductance amplifiers and a control unit which controls the gm values of the transconductance amplifiers. It limits the band of the signal output from a first filter signal selection unit, and outputs the result to the subsequent circuit.

Abstract: The collectors of transistors are connected via respective resistances to a power supply terminal receiving a power supply voltage. The emitters of the transistors are connected to a ground terminal via respective resistances. A shunt resistance, a FET, and a shunt resistance are connected in series between nodes connected to the respective emitters of the transistors. The gate of the FET is connected via a resistance to a control terminal receiving a control voltage. The shunt resistances and FET form a variable resistance circuit.

Abstract: An analog-to-digital conversion apparatus which has a variable resolution and allows a reduction in power consumption. This apparatus comprises an analog-to-digital converter (ADC) of parallel type, a controller, and an interpolation circuit. The analog-to-digital converter has a plurality of comparators connected in parallel, each for comparing potentials of an analog input signal and a reference signal. The controller generates a control signal for controlling the resolution of the analog-to-digital converter. Specifically, the controller controls the number of comparators (CMP) to operate by means of the control signal, thereby determining the resolution. The interpolation circuit interpolates the output data of the comparators that are disabled depending on the resolution. The controller avoids simultaneous operation of two adjoining comparators when the analog-to-digital converter is operated at a resolution lower than its maximum resolution.

Abstract: An FET is connected between the emitters of first and second transistors. The emitter of the first transistor is connected to a ground terminal through a plurality of resistors and the emitter of the second transistor is connected to the ground terminal through a plurality of resistors. Another FET is connected between a node between the plurality of resistors on one side and a node between the plurality of resistors on the other side. The gates of the FETs are connected to a control terminal receiving a control voltage through resistors respectively. The resistors and the FETs form a variable resistance circuit. Alternatively, two FETs are serially connected between nodes connected to the emitters of the first and second transistors. Another FET is connected between a node between the two FETs and a ground terminal. The gates of the two FETs are connected to a control terminal receiving a control voltage through resistors respectively.

Abstract: An FET is connected between the emitters of first and second transistors. The emitter of the first transistor is connected to a ground terminal through a plurality of resistors and the emitter of the second transistor is connected to the ground terminal through a plurality of resistors. Another FET is connected between a node between the plurality of resistors on one side and a node between the plurality of resistors on the other side. The gates of the FETs are connected to a control terminal receiving a control voltage through resistors respectively. The resistors and the FETs form a variable resistance circuit. Alternatively, two FETs are serially connected between nodes connected to the emitters of the first and second transistors. Another FET is connected between a node between the two FETs and a ground terminal. The gates of the two FETs are connected to a control terminal receiving a control voltage through resistors respectively.

Abstract: An FET is connected between the emitters of first and second transistors. The emitter of the first transistor is connected to a ground terminal through a plurality of resistors and the emitter of the second transistor is connected to the ground terminal through a plurality of resistors. Another FET is connected between a node between the plurality of resistors on one side and a node between the plurality of resistors on the other side. The gates of the FETs are connected to a control terminal receiving a control voltage through resistors respectively. The resistors and the FETs form a variable resistance circuit. Alternatively, two FETs are serially connected between nodes connected to the emitters of the first and second transistors. Another FET is connected between a node between the two FETs and a ground terminal. The gates of the two FETs are connected to a control terminal receiving a control voltage through resistors respectively.

Abstract: A first circuit which is constituted by a thin film resistor is connected between the collector of a transistor and a power supply terminal, and a second circuit which is constituted by a semiconductor resistor is connected between the emitter of the transistor and a grounding terminal. The film thickness of a thin film resistor is set to not more than its skin depth at a frequency to be compensated for.

Abstract: The collectors of transistors are connected via respective resistances to a power supply terminal receiving a power supply voltage. The emitters of the transistors are connected to a ground terminal via respective resistances. A shunt resistance, a FET, and a shunt resistance are connected in series between nodes connected to the respective emitters of the transistors. The gate of the FET is connected via a resistance to a control terminal receiving a control voltage. The shunt resistances and FET form a variable resistance circuit.

Abstract: An FET is connected between the emitters of first and second transistors. The emitter of the first transistor is connected to a ground terminal through a plurality of resistors and the emitter of the second transistor is connected to the ground terminal through a plurality of resistors. Another FET is connected between a node between the plurality of resistors on one side and a node between the plurality of resistors on the other side. The gates of the FETs are connected to a control terminal receiving a control voltage through resistors respectively. The resistors and the FETs form a variable resistance circuit. Alternatively, two FETs are serially connected between nodes connected to the emitters of the first and second transistors. Another FET is connected between a node between the two FETs and a ground terminal. The gates of the two FETs are connected to a control terminal receiving a control voltage through resistors respectively.

Abstract: An FET is connected between the emitters of first and second transistors. The emitter of the first transistor is connected to a ground terminal through a plurality of resistors and the emitter of the second transistor is connected to the ground terminal through a plurality of resistors. Another FET is connected between a node between the plurality of resistors on one side and a node between the plurality of resistors on the other side. The gates of the FETs are connected to a control terminal receiving a control voltage through resistors respectively. The resistors and the FETs form a variable resistance circuit. Alternatively, two FETs are serially connected between nodes connected to the emitters of the first and second transistors. Another FET is connected between a node between the two FETs and a ground terminal. The gates of the two FETs are connected to a control terminal receiving a control voltage through resistors respectively.

Abstract: A first circuit which is constituted by a thin film resistor is connected between the collector of a transistor and a power supply terminal, and a second circuit which is constituted by a semiconductor resistor is connected between the emitter of the transistor and a grounding terminal. The film thickness of a thin film resistor is set to not more than its skin depth at a frequency to be compensated for.

Abstract: A switching circuit device including a multi-gate field effect transistor having a plurality of gate electrodes between a drain electrode and a source electrode, a low resistor having its one end connected between the gate electrodes, and a high resistor connected between the other end of the low resistor and any one of the drain electrode, the source electrode and the end of the other low resistor.

Abstract: A optical divider equally divides a optical carrier into first and second optical carriers. A 180.degree. divider divides an RF sub-carrier signal into first and second RF sub-carrier signals whose phases are 180.degree. inverted from each other. An electro-optic modulator modulates the first optical carrier with the first RF sub-carrier signal and outputs a first optical signal. An electro-optic modulator modulates the second optical signal with the second RF sub-carrier signal and outputs a second optical signal. Photodiodes convert the first and second optical signals transmitted by the optical fibers into first and second electric signals, respectively. A 180.degree. combiner inverts by 180.degree. the phase of the first electric signal and combines it with the second electric signal.