Patents by Inventor Seiichi Hirata

Seiichi Hirata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6528347
    Abstract: In this disclosure, the semiconductor is directly mounted on the substrate plate of a package. According to this configuration, heat generated by the semiconductor chip is directly discharged, an excellent heat discharge property is realized. Moreover, the circuit is securely grounded and an excellent electric property is obtained.
    Type: Grant
    Filed: March 12, 2002
    Date of Patent: March 4, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Seiichi Hirata, Kazutaka Takagi
  • Publication number: 20020089068
    Abstract: In this disclosure, the semiconductor is directly mounted on the substrate plate of a package. According to this configuration, heat generated by the semiconductor chip is directly discharged, an excellent heat discharge property is realized. Moreover. the circuit is securely grounded and an excellent electric property is obtained.
    Type: Application
    Filed: March 12, 2002
    Publication date: July 11, 2002
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Seiichi Hirata, Kazutaka Takagi
  • Patent number: 6400035
    Abstract: In this disclosure, the semiconductor is directly mounted on the substrate plate of a package. According to this configuration, heat generated by the semiconductor chip is directly discharged, an excellent heat discharge property is realized. Moreover, the circuit is securely grounded and an excellent electric property is obtained.
    Type: Grant
    Filed: March 13, 2001
    Date of Patent: June 4, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Seiichi Hirata, Kazutaka Takagi
  • Publication number: 20020031859
    Abstract: In this disclosure, the semiconductor is directly mounted on the substrate plate of a package. According to this configuration, heat generated by the semiconductor chip is directly discharged, an excellent heat discharge property is realized. Moreover, the circuit is securely grounded and an excellent electric property is obtained.
    Type: Application
    Filed: March 13, 2001
    Publication date: March 14, 2002
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Seiichi Hirata, Kazutaka Takagi
  • Patent number: 5448451
    Abstract: Two device holes are formed in a base film such that the device holes are juxtaposed in a width direction of the base film perpendicular to a feed direction of the base film. An outer lead hole is formed in the base film with a distance from the device holes in the feed direction. A first lead wire group is arranged on the base film between the outer lead hole and one of the device holes, and a second lead wire group is arranged on the base film between the outer lead hole and the other device hole. Further, a third lead wire group is arranged on the base film between both device holes.
    Type: Grant
    Filed: November 19, 1993
    Date of Patent: September 5, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Chiaki Takubo, Kimihiro Ikebe, Masafumi Takeuchi, Seiichi Hirata, Sumio Takeda
  • Patent number: 5371406
    Abstract: According to this invention, there is provided a semiconductor device including a TAB tape having through hole for an element, a plurality of leads integrally formed on the TAB tape, a semiconductor element connected to one end of each of the leads through a bump formed in the through hole for the element, a plurality of lead frames each connected to the other end of a corresponding one of the leads, and a mold resin sealed to cover the most part of the TAB tape, the leads, the semiconductor element, and the lead frames, wherein connection portions between the leads and the lead frames are linearly formed at equal pitches perpendicularly to an outer periphery of the semiconductor element opposite to the connection portions. Each of portions near positions where the leads are respectively connected to the lead frames is formed in a gull-wing shape.
    Type: Grant
    Filed: July 27, 1993
    Date of Patent: December 6, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinjiro Kojima, Seiichi Hirata
  • Patent number: 5329068
    Abstract: An insulating film is formed on a semiconductor substrate, and an Al electrode pad is provided on the insulating film. The pad is electrically connected to a positive element by means of a signal line. A protection film is formed on the pad and insulating film. First and second openings are formed in the protection film. A barrier metal layer is formed on the inner periphery of the first opening and on the protection film. An Au bump is formed on the barrier metal layer. The Al electrode pad is exposed through the second opening.
    Type: Grant
    Filed: June 9, 1993
    Date of Patent: July 12, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Seiichi Hirata, Akito Yoshida
  • Patent number: 5291374
    Abstract: There is disclosed a semiconductor device having an insulating film formed on a substrate in which a semiconductor element is formed; an electrode pad is formed on the insulating film and is electrically connected to the semiconductor element by a signal line; an insulating protective film which covers the semiconductor substrate and has an opening for connecting an external circuit connection device to expose the surface of the electrode pad and an exposing opening, provided at peripheral portion of the electrode pad, for exposing a side of the electrode pad; and an external circuit connection device connected to the electrode pad via the opening for connecting.Since the side of the electrode pad can be exposed by forming an exposing opening in the insulating film, in the case where the inner lead is connected to the electrode pad via bump using ILB or the case where the wire bonding is applied to the electrode pad, the force applied to the electrode pad can be released by deformation of the electrode pad.
    Type: Grant
    Filed: August 17, 1992
    Date of Patent: March 1, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Seiichi Hirata, Akito Yoshida
  • Patent number: 5223739
    Abstract: A plastic molded semiconductor device having a semiconductor chip mounted on a die pad supported by hanging pins. The semiconductor chip is encapsulated by mold plastic where the semiconductor chip has a lead portion protruding to a side, and in which practically the entire periphery of the semiconductor chip is covered by aluminum or some other moistureproof material that stops the entry of moisture.
    Type: Grant
    Filed: September 13, 1990
    Date of Patent: June 29, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akio Katsumata, Seiichi Hirata, Shinetsu Fujieda, Hiroshi Shimozawa
  • Patent number: 4855807
    Abstract: This invention provides a semiconductor device comprising a die-pad supported by tie-bars, a semiconductor element mounted on the die-pad with the die-pad, tie-bars and semiconductor element being encapsulated in a moulding compound, means for defining an aperture which extends in to the moulding compound so as to expose a portion of a tie-bar.
    Type: Grant
    Filed: December 18, 1987
    Date of Patent: August 8, 1989
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuhiro Yamaji, Kenji Takahashi, Seiichi Hirata, Toshiharu Sakurai
  • Patent number: 4654692
    Abstract: Slits are formed in the metal wiring layer formed on the semiconductor of a semiconductor device to be resin sealed thereby to divide the total width of the metal wiring layer into divided widths each of the order of 30 to 40 .mu.m, whereby stress generated in the metal wiring layer is absorbed and prevented from causing cracking, deformation, and other defects. The slits are arranged to be substantially parallel to the peripheral side of the device which is most closely located to the wiring part.
    Type: Grant
    Filed: August 6, 1986
    Date of Patent: March 31, 1987
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiharu Sakurai, Seiichi Hirata