Patents by Inventor Seiichi Ichihara

Seiichi Ichihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160071769
    Abstract: In order to shield the light incident from the chip side surface or chip rear surface of a semiconductor chip that forms an LCD driver, a light-shielding film is formed over the chip side surface and chip rear surface of the semiconductor chip itself, not using a light-shielding tape that is a component separate from the semiconductor chip. Accordingly, the light-shielding tape as a separate component is not used, and hence the trouble that the light-shielding tape may protrude from the surface of a glass substrate whose thickness has been made small can be solved. As a result, the thinning of a liquid crystal display, and the subsequent thinning of the mobile phone in which the liquid crystal display is mounted can be promoted.
    Type: Application
    Filed: November 19, 2015
    Publication date: March 10, 2016
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Seiichi ICHIHARA, Hisao NAKAMURA
  • Patent number: 9224622
    Abstract: In order to shield the light incident from the chip side surface or chip rear surface of a semiconductor chip that forms an LCD driver, a light-shielding film is formed over the chip side surface and chip rear surface of the semiconductor chip itself, not using a light-shielding tape that is a component separate from the semiconductor chip. Accordingly, the light-shielding tape as a separate component is not used, and hence the trouble that the light-shielding tape may protrude from the surface of a glass substrate whose thickness has been made small can be solved. As a result, the thinning of a liquid crystal display, and the subsequent thinning of the mobile phone in which the liquid crystal display is mounted can be promoted.
    Type: Grant
    Filed: November 5, 2012
    Date of Patent: December 29, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Seiichi Ichihara, Hisao Nakamura
  • Patent number: 8708079
    Abstract: A vehicle body structure is provided with a vehicle body member, a charger, a structural support member. The charger includes an upper end portion and a lower end portion. The lower end portion of the charger is supported on the vehicle body member. The structural support member extends in a widthwise direction of the vehicle body structure in a position rearward of the upper end portion of the charger and adjacent the upper end portion of the charger.
    Type: Grant
    Filed: May 25, 2010
    Date of Patent: April 29, 2014
    Assignee: Nissan Motor Co., Ltd.
    Inventors: Tadayoshi Hashimura, Makoto Iwasa, Seiichi Ichihara, Nobuhiro Mori, Kenji Tamura
  • Patent number: 8587135
    Abstract: A semiconductor device has a conductive member coupled to the surface of a bonding pad exposed from an opening formed in a passivation film. A second planar distance between a first end of an electrode layer and a first end of a bonding pad is greater than a first planar distance between the first end of the electrode layer and a first end of an opening. Since the second planar distance between the first end of the electrode layer and the first end of the bonding pad is long, even when a coupled position of wire is deviated to the first end side of the electrode layer, stress caused by coupling of the wire to a stepped portion of the electrode layer can be prevented from being transmitted to the first end portion of the bonding pad.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: November 19, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Tamaki Wada, Akihiro Tobita, Seiichi Ichihara
  • Patent number: 8338288
    Abstract: In connection with a semiconductor device in which a conductive member is coupled to the surface of a bonding pad exposed from an opening formed in a passivation film, there is provided a technique able to suppress the occurrence of a crack in the passivation film. A second planar distance between a first end of an electrode layer and a first end of a pad is greater than a first planar distance between the first end of the electrode layer and a first end of an opening. Since the second planar distance between the first end of the electrode layer and the first end of the pad is long, even when a coupled position of wire is deviated to the first end side of the electrode layer, stress caused by coupling of the wire to a stepped portion of the electrode layer can be prevented from being transmitted to the first end portion of the pad.
    Type: Grant
    Filed: April 6, 2011
    Date of Patent: December 25, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Tamaki Wada, Akihiro Tobita, Seiichi Ichihara
  • Publication number: 20120049572
    Abstract: A vehicle body structure is provided with a vehicle body member, a charger, a structural support member. The charger includes an upper end portion and a lower end portion. The lower end portion of the charger is supported on the vehicle body member. The structural support member extends in a widthwise direction of the vehicle body structure in a position rearward of the upper end portion of the charger and adjacent the upper end portion of the charger.
    Type: Application
    Filed: May 25, 2010
    Publication date: March 1, 2012
    Applicant: NISSAN MOTOR CO., LTD.
    Inventors: Tadayoshi Hashimura, Makoto Iwasa, Seiichi Ichihara, Nobuhiro Mori, Kenji Tamura
  • Publication number: 20110248406
    Abstract: In connection with a semiconductor device in which a conductive member is coupled to the surface of a bonding pad exposed from an opening formed in a passivation film, there is provided a technique able to suppress the occurrence of a crack in the passivation film. A second planar distance between a first end of an electrode layer and a first end of a pad is greater than a first planar distance between the first end of the electrode layer and a first end of an opening. Since the second planar distance between the first end of the electrode layer and the first end of the pad is long, even when a coupled position of wire is deviated to the first end side of the electrode layer, stress caused by coupling of the wire to a stepped portion of the electrode layer can be prevented from being transmitted to the first end portion of the pad.
    Type: Application
    Filed: April 6, 2011
    Publication date: October 13, 2011
    Applicant: Renesas Electronics Corporation
    Inventors: Tamaki WADA, Akihiro TOBITA, Seiichi ICHIHARA
  • Patent number: 7470568
    Abstract: Salient electrodes on a semiconductor chip and leads on a film substrate are to be connected together with a high accuracy. A change in lead pitch which occurs at the time of connecting salient electrodes on a semiconductor chip and inner leads on a film substrate with each other is taken into account and a correction is made beforehand to the pitch of the inner leads. Likewise, a change in lead pitch which occurs at the time of connecting electrodes on a liquid crystal substrate and outer leads on the film substrate with each other is taken into account and a correction is made beforehand to the pitch of the outer leads.
    Type: Grant
    Filed: July 31, 2007
    Date of Patent: December 30, 2008
    Assignees: Renesas Technology Corporation, Hitachi ULSI Systems Co., Ltd.
    Inventors: Shinji Tojo, Shinya Kanamitsu, Seiichi Ichihara
  • Publication number: 20080090314
    Abstract: It is in offering the technology which can solve the problem actualized in connection with the narrowing of a pitch of a bump electrode. Concretely, even if it is a case where the contact position of the probe needle to a bump electrode shifts, in the needle contact of the probe needle in an electrical property test, the technology in which it can prevent that a probe needle contacts an adjoining bump electrode is offered. Bump electrodes are arranged in a single line, and they are arranged so that a partial area may shift in an adjoining bump electrode. And a probe needle is contacted to the region which has shifted and an electrical property test is carried out.
    Type: Application
    Filed: September 21, 2007
    Publication date: April 17, 2008
    Inventors: Seiichi Ichihara, Atsushi Obuchi
  • Publication number: 20080032453
    Abstract: Salient electrodes on a semiconductor chip and leads on a film substrate are to be connected together with a high accuracy. A change in lead pitch which occurs at the time of connecting salient electrodes on a semiconductor chip and inner leads on a film substrate with each other is taken into account and a correction is made beforehand to the pitch of the inner leads. Likewise, a change in lead pitch which occurs at the time of connecting electrodes on a liquid crystal substrate and outer leads on the film substrate with each other is taken into account and a correction is made beforehand to the pitch of the outer leads.
    Type: Application
    Filed: July 31, 2007
    Publication date: February 7, 2008
    Inventors: Shinji Tojo, Shinya Kanamitsu, Seiichi Ichihara
  • Patent number: 7262083
    Abstract: Salient electrodes on a semiconductor chip and leads on a film substrate are to be connected together with a high accuracy. A change in lead pitch which occurs at the time of connecting salient electrodes on a semiconductor chip and inner leads on a film substrate with each other is taken into account and a correction is made beforehand to the pitch of the inner leads. Likewise, a change in lead pitch which occurs at the time of connecting electrodes on a liquid crystal substrate and outer leads on the film substrate with each other is taken into account and a correction is made beforehand to the pitch of the outer leads.
    Type: Grant
    Filed: January 12, 2004
    Date of Patent: August 28, 2007
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Shinji Tojo, Shinya Kanamitsu, Seiichi Ichihara
  • Publication number: 20050167808
    Abstract: A semiconductor device comprising a semiconductor chip having an electrode on a circuit formation surface thereof, a flexible film having a lead attached thereto and electrically connected to said electrode of said semiconductor chip through a bump, a resin for covering said circuit formation surface of said semiconductor chip and a resin film for covering a back surface facing said circuit formation surface of said semiconductor chip.
    Type: Application
    Filed: March 30, 2005
    Publication date: August 4, 2005
    Inventors: Masako Sasaki, Kazunari Suzuki, Seiichi Ichihara, Tomoaki Kudaishi, Hisao Nakamura, Kunihiko Nishi, Hideki Tanaka, Yutaka Nakajima
  • Publication number: 20040142512
    Abstract: Salient electrodes on a semiconductor chip and leads on a film substrate are to be connected together with a high accuracy. A change in lead pitch which occurs at the time of connecting salient electrodes on a semiconductor chip and inner leads on a film substrate with each other is taken into account and a correction is made beforehand to the pitch of the inner leads. Likewise, a change in lead pitch which occurs at the time of connecting electrodes on a liquid crystal substrate and outer leads on the film substrate with each other is taken into account and a correction is made beforehand to the pitch of the outer leads.
    Type: Application
    Filed: January 12, 2004
    Publication date: July 22, 2004
    Applicants: Renesas Technology Corporation, Hitachi ULSI Systems Co., Ltd.
    Inventors: Shinji Tojo, Shinya Kanamitsu, Seiichi Ichihara
  • Patent number: 6699737
    Abstract: Salient electrodes on a semiconductor chip and leads on a film substrate are to be connected together with a high accuracy. A change in lead pitch which occurs at the time of connecting salient electrodes on a semiconductor chip and inner leads on a film substrate with each other is taken into account and a correction is made beforehand to the pitch of the inner leads. Likewise, a change in lead pitch which occurs at the time of connecting electrodes on a liquid crystal substrate and outer leads on the film substrate with each other is taken into account and a correction is made beforehand to the pitch of the outer leads.
    Type: Grant
    Filed: September 13, 2002
    Date of Patent: March 2, 2004
    Assignees: Renesas Technology Corporation, Hitachi ULSI Systems Co., Ltd.
    Inventors: Shinji Tojo, Shinya Kanamitsu, Seiichi Ichihara
  • Patent number: 6645794
    Abstract: In a semiconductor device manufacturing method in which a package including a semiconductor chip is mounted on a wiring board via tape ball grid array (TBGA), a tape base material having a device hole and a plurality of leads is provided with one end of the leads extended inside the device hole and a part of the other end of the leads forming lands for connecting bump electrodes. The semiconductor chip is arranged in the device hole of the tape base material to electrically connect the semiconductor chip and the one end of the leads. A sealing resin and reinforcing frame surrounding the periphery of the sealing resin are monolithically formed by transfer molding. The tape base material is fixed in an area between the semiconductor chip and the reinforcing frame by a lower mold and a projection of an upper mold.
    Type: Grant
    Filed: November 25, 2002
    Date of Patent: November 11, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Noriyuki Takahashi, Seiichi Ichihara, Chuichi Miyazaki
  • Publication number: 20030073266
    Abstract: A semiconductor device according to the invention is TBGA comprised of a semiconductor chip (3) mounted on a wiring board (2) on which plural leads (1) are formed and electrically connected to one end of the lead (1), sealing resin (4) for coating the semiconductor chip (3), a reinforcing frame (5) provided along the periphery of the wiring board and plural solder bumps (6) arranged along the periphery of the wiring board and electrically connected to the other end of the lead (1), and the sealing resin (4) and the reinforcing frame (5) are made of synthetic resin formed by transfer molding.
    Type: Application
    Filed: November 25, 2002
    Publication date: April 17, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Noriyuki Takahashi, Seiichi Ichihara, Chuichi Miyazaki
  • Publication number: 20030068842
    Abstract: Salient electrodes on a semiconductor chip and leads on a film substrate are to be connected together with a high accuracy. A change in lead pitch which occurs at the time of connecting salient electrodes on a semiconductor chip and inner leads on a film substrate with each other is taken into account and a correction is made beforehand to the pitch of the inner leads. Likewise, a change in lead pitch which occurs at the time of connecting electrodes on a liquid crystal substrate and outer leads on the film substrate with each other is taken into account and a correction is made beforehand to the pitch of the outer leads.
    Type: Application
    Filed: September 13, 2002
    Publication date: April 10, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Shinji Tojo, Shinya Kanamitsu, Seiichi Ichihara
  • Publication number: 20030017652
    Abstract: A semiconductor device comprising a semiconductor chip having an electrode on a circuit formation surface thereof, a flexible film having a lead attached thereto and electrically connected to said electrode of said semiconductor chip through a bump, a resin for covering said circuit formation surface of said semiconductor chip and a resin film for covering a back surface facing said circuit formation surface of said semiconductor chip.
    Type: Application
    Filed: September 24, 2002
    Publication date: January 23, 2003
    Inventors: Masako Sakaki, Kazunari Suzuki, Seiichi Ichihara, Tomoaki Kudaishi, Hisao Nakamura, Kunihiko Nishi, Hideki Tanaka, Yutaka Nakajima
  • Patent number: 6476467
    Abstract: The thickness of a tape carrier package having a semiconductor chip is made uniform where bonding pads are concentrated on one side of the semiconductor chip. The tape carrier package is such that dummy pads 6b are arranged on one side opposite to the side on which bonding pads (effective pins) 6a are arranged in the semiconductor chip. Dummy leads 5 are formed on an insulating tape 4. The semiconductor chip is supported with inner lead portions 5a connected to the corresponding bonding pads 6a and the inner lead portions 5a of the dummy leads 5 connected to the corresponding dummy pads 6b.
    Type: Grant
    Filed: June 1, 2001
    Date of Patent: November 5, 2002
    Assignees: Hitachi, Ltd., Hitachi Microcomputer Systems Ltd.
    Inventors: Hisao Nakamura, Seiichi Ichihara, Ryosuke Kimoto, Hiroshi Kawakubo, Ryo Haruta, Hiroshi Koyama
  • Publication number: 20020149027
    Abstract: A semiconductor device comprising a semiconductor chip, a wiring substrate provided surrounding the semiconductor chip, leads projected from the wiring substrate and connected to the semiconductor chip, a stiffening member provided on one main surface of the wiring substrate, surrounding-the semiconductor chip, a plurality of bumps provided along a periphery of the wiring substrate on another main surface of the wiring substrate opposite to the main surface where the stiffening member is provided, and resin covering the semiconductor chip and the leads. The leads connected to the semiconductor chip are bend-processed toward a side where the stiffening member of the wiring substrate is provided or a side where the plurality of bumps are formed. The leads and the semiconductor chip are connected such that the surface of the semiconductor chip opposite to the surface connected to the leads is positioned on a side opposite to the side where the leads are bend-processed.
    Type: Application
    Filed: September 17, 1999
    Publication date: October 17, 2002
    Inventors: NORIYUKI TAKAHASHI, SEIICHI ICHIHARA, CHUICHI MIYAZAKI