Patents by Inventor Seiichi Ichihara
Seiichi Ichihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160071769Abstract: In order to shield the light incident from the chip side surface or chip rear surface of a semiconductor chip that forms an LCD driver, a light-shielding film is formed over the chip side surface and chip rear surface of the semiconductor chip itself, not using a light-shielding tape that is a component separate from the semiconductor chip. Accordingly, the light-shielding tape as a separate component is not used, and hence the trouble that the light-shielding tape may protrude from the surface of a glass substrate whose thickness has been made small can be solved. As a result, the thinning of a liquid crystal display, and the subsequent thinning of the mobile phone in which the liquid crystal display is mounted can be promoted.Type: ApplicationFiled: November 19, 2015Publication date: March 10, 2016Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Seiichi ICHIHARA, Hisao NAKAMURA
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Patent number: 9224622Abstract: In order to shield the light incident from the chip side surface or chip rear surface of a semiconductor chip that forms an LCD driver, a light-shielding film is formed over the chip side surface and chip rear surface of the semiconductor chip itself, not using a light-shielding tape that is a component separate from the semiconductor chip. Accordingly, the light-shielding tape as a separate component is not used, and hence the trouble that the light-shielding tape may protrude from the surface of a glass substrate whose thickness has been made small can be solved. As a result, the thinning of a liquid crystal display, and the subsequent thinning of the mobile phone in which the liquid crystal display is mounted can be promoted.Type: GrantFiled: November 5, 2012Date of Patent: December 29, 2015Assignee: Renesas Electronics CorporationInventors: Seiichi Ichihara, Hisao Nakamura
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Patent number: 8708079Abstract: A vehicle body structure is provided with a vehicle body member, a charger, a structural support member. The charger includes an upper end portion and a lower end portion. The lower end portion of the charger is supported on the vehicle body member. The structural support member extends in a widthwise direction of the vehicle body structure in a position rearward of the upper end portion of the charger and adjacent the upper end portion of the charger.Type: GrantFiled: May 25, 2010Date of Patent: April 29, 2014Assignee: Nissan Motor Co., Ltd.Inventors: Tadayoshi Hashimura, Makoto Iwasa, Seiichi Ichihara, Nobuhiro Mori, Kenji Tamura
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Patent number: 8587135Abstract: A semiconductor device has a conductive member coupled to the surface of a bonding pad exposed from an opening formed in a passivation film. A second planar distance between a first end of an electrode layer and a first end of a bonding pad is greater than a first planar distance between the first end of the electrode layer and a first end of an opening. Since the second planar distance between the first end of the electrode layer and the first end of the bonding pad is long, even when a coupled position of wire is deviated to the first end side of the electrode layer, stress caused by coupling of the wire to a stepped portion of the electrode layer can be prevented from being transmitted to the first end portion of the bonding pad.Type: GrantFiled: November 21, 2012Date of Patent: November 19, 2013Assignee: Renesas Electronics CorporationInventors: Tamaki Wada, Akihiro Tobita, Seiichi Ichihara
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Patent number: 8338288Abstract: In connection with a semiconductor device in which a conductive member is coupled to the surface of a bonding pad exposed from an opening formed in a passivation film, there is provided a technique able to suppress the occurrence of a crack in the passivation film. A second planar distance between a first end of an electrode layer and a first end of a pad is greater than a first planar distance between the first end of the electrode layer and a first end of an opening. Since the second planar distance between the first end of the electrode layer and the first end of the pad is long, even when a coupled position of wire is deviated to the first end side of the electrode layer, stress caused by coupling of the wire to a stepped portion of the electrode layer can be prevented from being transmitted to the first end portion of the pad.Type: GrantFiled: April 6, 2011Date of Patent: December 25, 2012Assignee: Renesas Electronics CorporationInventors: Tamaki Wada, Akihiro Tobita, Seiichi Ichihara
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Publication number: 20120049572Abstract: A vehicle body structure is provided with a vehicle body member, a charger, a structural support member. The charger includes an upper end portion and a lower end portion. The lower end portion of the charger is supported on the vehicle body member. The structural support member extends in a widthwise direction of the vehicle body structure in a position rearward of the upper end portion of the charger and adjacent the upper end portion of the charger.Type: ApplicationFiled: May 25, 2010Publication date: March 1, 2012Applicant: NISSAN MOTOR CO., LTD.Inventors: Tadayoshi Hashimura, Makoto Iwasa, Seiichi Ichihara, Nobuhiro Mori, Kenji Tamura
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Publication number: 20110248406Abstract: In connection with a semiconductor device in which a conductive member is coupled to the surface of a bonding pad exposed from an opening formed in a passivation film, there is provided a technique able to suppress the occurrence of a crack in the passivation film. A second planar distance between a first end of an electrode layer and a first end of a pad is greater than a first planar distance between the first end of the electrode layer and a first end of an opening. Since the second planar distance between the first end of the electrode layer and the first end of the pad is long, even when a coupled position of wire is deviated to the first end side of the electrode layer, stress caused by coupling of the wire to a stepped portion of the electrode layer can be prevented from being transmitted to the first end portion of the pad.Type: ApplicationFiled: April 6, 2011Publication date: October 13, 2011Applicant: Renesas Electronics CorporationInventors: Tamaki WADA, Akihiro TOBITA, Seiichi ICHIHARA
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Patent number: 7470568Abstract: Salient electrodes on a semiconductor chip and leads on a film substrate are to be connected together with a high accuracy. A change in lead pitch which occurs at the time of connecting salient electrodes on a semiconductor chip and inner leads on a film substrate with each other is taken into account and a correction is made beforehand to the pitch of the inner leads. Likewise, a change in lead pitch which occurs at the time of connecting electrodes on a liquid crystal substrate and outer leads on the film substrate with each other is taken into account and a correction is made beforehand to the pitch of the outer leads.Type: GrantFiled: July 31, 2007Date of Patent: December 30, 2008Assignees: Renesas Technology Corporation, Hitachi ULSI Systems Co., Ltd.Inventors: Shinji Tojo, Shinya Kanamitsu, Seiichi Ichihara
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Publication number: 20080090314Abstract: It is in offering the technology which can solve the problem actualized in connection with the narrowing of a pitch of a bump electrode. Concretely, even if it is a case where the contact position of the probe needle to a bump electrode shifts, in the needle contact of the probe needle in an electrical property test, the technology in which it can prevent that a probe needle contacts an adjoining bump electrode is offered. Bump electrodes are arranged in a single line, and they are arranged so that a partial area may shift in an adjoining bump electrode. And a probe needle is contacted to the region which has shifted and an electrical property test is carried out.Type: ApplicationFiled: September 21, 2007Publication date: April 17, 2008Inventors: Seiichi Ichihara, Atsushi Obuchi
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Publication number: 20080032453Abstract: Salient electrodes on a semiconductor chip and leads on a film substrate are to be connected together with a high accuracy. A change in lead pitch which occurs at the time of connecting salient electrodes on a semiconductor chip and inner leads on a film substrate with each other is taken into account and a correction is made beforehand to the pitch of the inner leads. Likewise, a change in lead pitch which occurs at the time of connecting electrodes on a liquid crystal substrate and outer leads on the film substrate with each other is taken into account and a correction is made beforehand to the pitch of the outer leads.Type: ApplicationFiled: July 31, 2007Publication date: February 7, 2008Inventors: Shinji Tojo, Shinya Kanamitsu, Seiichi Ichihara
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Patent number: 7262083Abstract: Salient electrodes on a semiconductor chip and leads on a film substrate are to be connected together with a high accuracy. A change in lead pitch which occurs at the time of connecting salient electrodes on a semiconductor chip and inner leads on a film substrate with each other is taken into account and a correction is made beforehand to the pitch of the inner leads. Likewise, a change in lead pitch which occurs at the time of connecting electrodes on a liquid crystal substrate and outer leads on the film substrate with each other is taken into account and a correction is made beforehand to the pitch of the outer leads.Type: GrantFiled: January 12, 2004Date of Patent: August 28, 2007Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Shinji Tojo, Shinya Kanamitsu, Seiichi Ichihara
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Publication number: 20050167808Abstract: A semiconductor device comprising a semiconductor chip having an electrode on a circuit formation surface thereof, a flexible film having a lead attached thereto and electrically connected to said electrode of said semiconductor chip through a bump, a resin for covering said circuit formation surface of said semiconductor chip and a resin film for covering a back surface facing said circuit formation surface of said semiconductor chip.Type: ApplicationFiled: March 30, 2005Publication date: August 4, 2005Inventors: Masako Sasaki, Kazunari Suzuki, Seiichi Ichihara, Tomoaki Kudaishi, Hisao Nakamura, Kunihiko Nishi, Hideki Tanaka, Yutaka Nakajima
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Publication number: 20040142512Abstract: Salient electrodes on a semiconductor chip and leads on a film substrate are to be connected together with a high accuracy. A change in lead pitch which occurs at the time of connecting salient electrodes on a semiconductor chip and inner leads on a film substrate with each other is taken into account and a correction is made beforehand to the pitch of the inner leads. Likewise, a change in lead pitch which occurs at the time of connecting electrodes on a liquid crystal substrate and outer leads on the film substrate with each other is taken into account and a correction is made beforehand to the pitch of the outer leads.Type: ApplicationFiled: January 12, 2004Publication date: July 22, 2004Applicants: Renesas Technology Corporation, Hitachi ULSI Systems Co., Ltd.Inventors: Shinji Tojo, Shinya Kanamitsu, Seiichi Ichihara
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Patent number: 6699737Abstract: Salient electrodes on a semiconductor chip and leads on a film substrate are to be connected together with a high accuracy. A change in lead pitch which occurs at the time of connecting salient electrodes on a semiconductor chip and inner leads on a film substrate with each other is taken into account and a correction is made beforehand to the pitch of the inner leads. Likewise, a change in lead pitch which occurs at the time of connecting electrodes on a liquid crystal substrate and outer leads on the film substrate with each other is taken into account and a correction is made beforehand to the pitch of the outer leads.Type: GrantFiled: September 13, 2002Date of Patent: March 2, 2004Assignees: Renesas Technology Corporation, Hitachi ULSI Systems Co., Ltd.Inventors: Shinji Tojo, Shinya Kanamitsu, Seiichi Ichihara
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Patent number: 6645794Abstract: In a semiconductor device manufacturing method in which a package including a semiconductor chip is mounted on a wiring board via tape ball grid array (TBGA), a tape base material having a device hole and a plurality of leads is provided with one end of the leads extended inside the device hole and a part of the other end of the leads forming lands for connecting bump electrodes. The semiconductor chip is arranged in the device hole of the tape base material to electrically connect the semiconductor chip and the one end of the leads. A sealing resin and reinforcing frame surrounding the periphery of the sealing resin are monolithically formed by transfer molding. The tape base material is fixed in an area between the semiconductor chip and the reinforcing frame by a lower mold and a projection of an upper mold.Type: GrantFiled: November 25, 2002Date of Patent: November 11, 2003Assignee: Hitachi, Ltd.Inventors: Noriyuki Takahashi, Seiichi Ichihara, Chuichi Miyazaki
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Publication number: 20030073266Abstract: A semiconductor device according to the invention is TBGA comprised of a semiconductor chip (3) mounted on a wiring board (2) on which plural leads (1) are formed and electrically connected to one end of the lead (1), sealing resin (4) for coating the semiconductor chip (3), a reinforcing frame (5) provided along the periphery of the wiring board and plural solder bumps (6) arranged along the periphery of the wiring board and electrically connected to the other end of the lead (1), and the sealing resin (4) and the reinforcing frame (5) are made of synthetic resin formed by transfer molding.Type: ApplicationFiled: November 25, 2002Publication date: April 17, 2003Applicant: Hitachi, Ltd.Inventors: Noriyuki Takahashi, Seiichi Ichihara, Chuichi Miyazaki
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Publication number: 20030068842Abstract: Salient electrodes on a semiconductor chip and leads on a film substrate are to be connected together with a high accuracy. A change in lead pitch which occurs at the time of connecting salient electrodes on a semiconductor chip and inner leads on a film substrate with each other is taken into account and a correction is made beforehand to the pitch of the inner leads. Likewise, a change in lead pitch which occurs at the time of connecting electrodes on a liquid crystal substrate and outer leads on the film substrate with each other is taken into account and a correction is made beforehand to the pitch of the outer leads.Type: ApplicationFiled: September 13, 2002Publication date: April 10, 2003Applicant: Hitachi, Ltd.Inventors: Shinji Tojo, Shinya Kanamitsu, Seiichi Ichihara
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Publication number: 20030017652Abstract: A semiconductor device comprising a semiconductor chip having an electrode on a circuit formation surface thereof, a flexible film having a lead attached thereto and electrically connected to said electrode of said semiconductor chip through a bump, a resin for covering said circuit formation surface of said semiconductor chip and a resin film for covering a back surface facing said circuit formation surface of said semiconductor chip.Type: ApplicationFiled: September 24, 2002Publication date: January 23, 2003Inventors: Masako Sakaki, Kazunari Suzuki, Seiichi Ichihara, Tomoaki Kudaishi, Hisao Nakamura, Kunihiko Nishi, Hideki Tanaka, Yutaka Nakajima
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Patent number: 6476467Abstract: The thickness of a tape carrier package having a semiconductor chip is made uniform where bonding pads are concentrated on one side of the semiconductor chip. The tape carrier package is such that dummy pads 6b are arranged on one side opposite to the side on which bonding pads (effective pins) 6a are arranged in the semiconductor chip. Dummy leads 5 are formed on an insulating tape 4. The semiconductor chip is supported with inner lead portions 5a connected to the corresponding bonding pads 6a and the inner lead portions 5a of the dummy leads 5 connected to the corresponding dummy pads 6b.Type: GrantFiled: June 1, 2001Date of Patent: November 5, 2002Assignees: Hitachi, Ltd., Hitachi Microcomputer Systems Ltd.Inventors: Hisao Nakamura, Seiichi Ichihara, Ryosuke Kimoto, Hiroshi Kawakubo, Ryo Haruta, Hiroshi Koyama
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Publication number: 20020149027Abstract: A semiconductor device comprising a semiconductor chip, a wiring substrate provided surrounding the semiconductor chip, leads projected from the wiring substrate and connected to the semiconductor chip, a stiffening member provided on one main surface of the wiring substrate, surrounding-the semiconductor chip, a plurality of bumps provided along a periphery of the wiring substrate on another main surface of the wiring substrate opposite to the main surface where the stiffening member is provided, and resin covering the semiconductor chip and the leads. The leads connected to the semiconductor chip are bend-processed toward a side where the stiffening member of the wiring substrate is provided or a side where the plurality of bumps are formed. The leads and the semiconductor chip are connected such that the surface of the semiconductor chip opposite to the surface connected to the leads is positioned on a side opposite to the side where the leads are bend-processed.Type: ApplicationFiled: September 17, 1999Publication date: October 17, 2002Inventors: NORIYUKI TAKAHASHI, SEIICHI ICHIHARA, CHUICHI MIYAZAKI