Patents by Inventor Seiichi Isomae

Seiichi Isomae has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7189278
    Abstract: A method for producing semiconductor or metal particles comprises the steps of: storing a semiconductor or metal melt in a crucible having a nozzle; supplying a gas comprising at least one selected from the group consisting of He, Ne, Ar, Kr and Xe into the crucible such that the pressure of the supplied gas in a space over the melt in the crucible is higher than the pressure of a gaseous phase into which the melt is dropped; dropping the melt from the nozzle into the gaseous phase by the pressure of the gas to form liquid particles; and solidifying the liquid particles in the gaseous phase to obtain semiconductor or metal particles. The crucible comprises at least one selected from the group consisting of hexagonal BN, cubic BN, Si3N4, TiB2, ZrB2, zirconia and stabilized zirconia at least near the nozzle.
    Type: Grant
    Filed: April 18, 2003
    Date of Patent: March 13, 2007
    Assignee: Clean Venture 21 Corporation
    Inventors: Kenji Kato, Yukio Yamaguchi, Seiichi Isomae, Masaki Miyazaki
  • Publication number: 20040007790
    Abstract: A method for producing semiconductor or metal particles comprises the steps of: storing a semiconductor or metal melt in a crucible having a nozzle; supplying a gas comprising at least one selected from the group consisting of He, Ne, Ar, Kr and Xe into the crucible such that the pressure of the supplied gas in a space over the melt in the crucible is higher than the pressure of a gaseous phase into which the melt is dropped; dropping the melt from the nozzle into the gaseous phase by the pressure of the gas to form liquid particles; and solidifying the liquid particles in the gaseous phase to obtain semiconductor or metal particles. The crucible comprises at least one selected from the group consisting of hexagonal BN, cubic BN, Si3N4, TiB2, ZrB2, zirconia and stabilized zirconia at least near the nozzle.
    Type: Application
    Filed: April 18, 2003
    Publication date: January 15, 2004
    Inventors: Kenji Kato, Yukio Yamaguchi, Seiichi Isomae, Masaki Miyazaki
  • Patent number: 6635950
    Abstract: To improve the gettering performance by ion implanting boron and improves the production yield of the semiconductor device by using an epitaxial wafer of good quality suppressing the occurrence of dislocations. For this purpose, an epitaxial wafer in which an epitaxial layer of about 1 &mgr;m is formed to a CZ semiconductor substrate implanted with boron ions which are dopant and carbon ions which are not a dopant is provided, and transistors are formed on the surface of the epitaxial layer.
    Type: Grant
    Filed: September 19, 2000
    Date of Patent: October 21, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Hidetsugu Ishida, Seiichi Isomae
  • Patent number: 6226079
    Abstract: A defect assessing apparatus and method and a semiconductor manufacturing method for revealing the relationship between the size and depth of defects is disclosed. A detecting optical system is provided for detecting the intensity of scattered light from a defect generated by the shorter wavelength one of the light rays of at least two different wavelengths emitted from irradiating optical systems and that of scattered light from the defect generated by the longer wavelength one of same. A calculating means is provided for determining, from the scattered light intensity derived from the shorter wavelength ray and that derived form the longer wavelength ray, both detected by the detecting optical system, a value corresponding to the defect size and another value corresponding to the defect depth.
    Type: Grant
    Filed: September 29, 1998
    Date of Patent: May 1, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Kazuo Takeda, Makoto Ohkura, Seiichi Isomae, Kyoko Minowa, Muneo Maeshima, Shigeru Matsui, Yasushi Matsuda, Hirofumi Shimizu
  • Patent number: 6198157
    Abstract: To improve the gettering performance by ion implanting boron and improves the production yield of the semiconductor device by using an epitaxial wafer of good quality suppressing the occurrence of dislocations. For this purpose, an epitaxial wafer in which an epitaxial layer of about 1 &mgr;m is formed to a CZ semiconductor substrate implanted with boron ions which are dopant and carbon ions which are not a dopant is provided, and transistors are formed on the surface of the epitaxial layer.
    Type: Grant
    Filed: February 17, 1998
    Date of Patent: March 6, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Hidetsugu Ishida, Seiichi Isomae
  • Patent number: 4768076
    Abstract: A CMOS IC is formed on a semiconductor crystalline surface having a plane azimuth (110) or (023), or of a plane azimuth close thereto (plane azimuth substantially in parallel with the above-mentioned planes), in order to increase the speed of operation.At low temperatures, dependency of the carrier mobility upon the plane azimuth becomes more conspicuous as shown in FIG. 1, and the difference of mobility is amplified depending upon the planes. Therefore, employment of the above-mentioned crystalline planes helps produce a great effect when the CMOS device is to be operated at low temperature (e.g., 100.degree. K. or lower), and helps operate the device at high speeds.
    Type: Grant
    Filed: September 11, 1985
    Date of Patent: August 30, 1988
    Assignee: Hitachi, Ltd.
    Inventors: Masaaki Aoki, Toshiaki Masuhara, Terunori Warabisako, Shoji Hanamura, Yoshio Sakai, Seiichi Isomae, Satoshi Meguro, Shuji Ikeda
  • Patent number: 4126880
    Abstract: A germanium-containing silicon nitride film has a germanium content of 0.5 to 10 atomic-% that of the silicon content. Since the film has a much smaller stress than a conventional silicon nitride (Si.sub.3 N.sub.4) film, it is very suitable as a mask for fabricating a semiconductor device and an insulating or a protective film for a semiconductor device.
    Type: Grant
    Filed: January 4, 1977
    Date of Patent: November 21, 1978
    Assignee: Hitachi, Ltd.
    Inventors: Yoichi Tamaki, Seiichi Isomae, Masahiko Ogirima, Akira Shintani, Michiyoshi Maki