Patents by Inventor Seiichi Kaise

Seiichi Kaise has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7245987
    Abstract: At a time Tp when a wafer W is transferred into either a load lock chamber LL1 or LL2, periods PSL for the load lock chambers LL1 and LL2 to get ready to permit a transfer of a next wafer W thereinto are calculated based on a timing for exchange of wafers W between the load lock chamber LL1 or LL2 and a loader module LM. When the periods PSL are calculated, a loader arm LA1 or LA2 selects a next wafer W having the shortest period to get ready to be transferable into the load lock chamber LL1 or LL2, from load ports LP1 to LP3. This improves transfer delay in a cluster tool provided with the load lock chambers.
    Type: Grant
    Filed: May 16, 2005
    Date of Patent: July 17, 2007
    Assignee: Tokyo Electron Limited
    Inventors: Kiyohito Iijima, Seiichi Kaise, Keiko Takahashi, Akira Obi
  • Publication number: 20070009649
    Abstract: A substrate processing apparatus includes a heat transfer gas supply mechanism to supply a heat transfer gas through a supply passage into a portion between a worktable and a substrate to improve thermal conductivity between therebetween. Under the control of a control section, the pressure inside the supply passage is measured to obtain a pressure measurement value while the substrate is placed on the worktable. Then, a preparatory flow rate of the heat transfer gas to be supplied through the supply passage into the portion between the worktable and substrate is determined, in accordance with the pressure difference between the pressure measurement value and a pressure reference value, prior to a main process to be performed on the substrate. Then, the heat transfer gas is supplied through the supply passage into the portion between the worktable and substrate at the preparatory flow rate, prior to the main process.
    Type: Application
    Filed: June 2, 2006
    Publication date: January 11, 2007
    Inventors: Hiroshi Nakamura, Seiichi Kaise
  • Publication number: 20060176928
    Abstract: A substrate processing apparatus according to the present invention comprises a plurality of processing chambers, discharge systems each provided in conjunction with one of the processing chambers and a common discharge system connected with the discharge systems of at least two processing chambers among the discharge systems provided in conjunction with the individual processing chambers. The common discharge allows a switch-over between a scrubbing common discharge system that discharges discharge gas from each processing chamber after scrubbing the discharge gas at a scrubbing means and a non-scrubbing common discharge system that directly discharges the discharge gas from the discharge system of the processing chamber without scrubbing at the scrubbing means.
    Type: Application
    Filed: February 7, 2006
    Publication date: August 10, 2006
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Hiroshi Nakamura, Toshiyuki Kobayashi, Shinichiro Hayasaka, Seiichi Kaise
  • Publication number: 20060090703
    Abstract: A substrate processing method is used for a substrate processing system having a substrate processing device and a substrate transfer device. The substrate processing method includes a substrate transfer step of transferring a substrate and a substrate processing step of performing a predetermined process on the substrate. The substrate transfer step and the substrate processing step include a plurality of operations, and at least two operations among the plurality of the operations are performed simultaneously. Preferably, the substrate processing device includes an accommodating chamber, a mounting table placed in the accommodating chamber to be mounted thereon the substrate, and a heat transfer gas supply line for supplying a heat transfer gas to a space between the substrate mounted on the mounting table and the mounting table.
    Type: Application
    Filed: November 1, 2005
    Publication date: May 4, 2006
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Seiichi Kaise, Noriyuki Iwabuchi, Shigeaki Kato, Hiroshi Nakamura, Takeshi Yokouchi, Mariko Shibata, Akira Obi
  • Patent number: 6970770
    Abstract: At a time Tp when a wafer W is transferred into either a load lock chamber LL1 or LL2, periods PSL for the load lock chambers LL1 and LL2 to get ready to permit a transfer of a next wafer W thereinto are calculated based on a timing for exchange of wafers W between the load lock chamber LL1 or LL2 and a loader module LM. When the periods PSL are calculated, a loader arm LA1 or LA2 selects a next wafer W having the shortest period to get ready to be transferable into the load lock chamber LL1 or LL2, from load ports LP1 to LP3. This improves transfer delay in a cluster tool provided with the load lock chambers.
    Type: Grant
    Filed: April 2, 2002
    Date of Patent: November 29, 2005
    Assignee: Tokyo Electron Limited
    Inventors: Kiyohito Iljima, Seiichi Kaise, Keiko Takahashi, Akira Obi
  • Publication number: 20050220577
    Abstract: At a time Tp when a wafer W is transferred into either a load lock chamber LL1 or LL2, periods PSL for the load lock chambers LL1 and LL2 to get ready to permit a transfer of a next wafer W thereinto are calculated based on a timing for exchange of wafers W between the load lock chamber LL1 or LL2 and a loader module LM. When the periods PSL are calculated, a loader arm LA1 or LA2 selects a next wafer W having the shortest period to get ready to be transferable into the load lock chamber LL1 or LL2, from load ports LP1 to LP3. This improves transfer delay in a cluster tool provided with the load lock chambers.
    Type: Application
    Filed: May 16, 2005
    Publication date: October 6, 2005
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Kiyohito Iijima, Seiichi Kaise, Keiko Takahashi, Akira Obi
  • Publication number: 20040117059
    Abstract: At a time Tp when a wafer W is transferred into either a load lock chamber LL1 or LL2, periods PSL for the load lock chambers LL1 and LL2 to get ready to permit a transfer of a next wafer W thereinto are calculated based on a timing for exchange of wafers W between the load lock chamber LL1 or LL2 and a loader module LM. When the periods PSL are calculated, a loader arm LA1 or LA2 selects a next wafer W having the shortest period to get ready to be transferable into the load lock chamber LL1 or LL2, from load ports LP1 to LP3. This improves transfer delay in a cluster tool provided with the load lock chambers.
    Type: Application
    Filed: October 6, 2003
    Publication date: June 17, 2004
    Inventors: Kiyohito IIjima, Seiichi Kaise, Keiko Takahashi, Akira Obi