Abstract: Embodiments of a display device for displaying a marked image on a display device are disclosed. The display device includes a control circuit configured to receive image data and supplementary data, and a display panel. The display panel includes a plurality of main pixels, each of the plurality of main pixels including a main pixel electrode and configured to display the image data, and a plurality of supplementary pixels, each of the plurality of supplementary pixels including a supplementary pixel electrode and configured to display the supplementary data. The plurality of main pixel electrodes are arranged in a series of columns and rows to form a matrix with the plurality of supplementary pixel electrodes being interspersed within the matrix. The plurality of main pixels are larger in size than the plurality of supplementary pixels.

Abstract: Embodiments of a display device for displaying a marked image on a display device are disclosed. The display device includes a control circuit configured to receive image data and supplementary data, and a display panel. The display panel includes a plurality of main pixels, each of the plurality of main pixels including a main pixel electrode and configured to display the image data, and a plurality of supplementary pixels, each of the plurality of supplementary pixels including a supplementary pixel electrode and configured to display the supplementary data. The plurality of main pixel electrodes are arranged in a series of columns and rows to form a matrix with the plurality of supplementary pixel electrodes being interspersed within the matrix. The plurality of main pixels are larger in size than the plurality of supplementary pixels.

Abstract: A liquid crystal display device including a liquid crystal panel including liquid crystal sealed between a pair of substrates; a plurality of gate signal lines and a plurality of drain signal lines formed to cross each other on one of said pair of substrates; a pixel region surrounded by a pair of adjacent gate signal lines and a pair of adjacent drain signal lines; a thin film transistor provided in the pixel region and connected to at least one of the pair of adjacent gate signal lines and at least one of the pair of drain signal lines; a pixel electrode provided in the pixel region and supplied with a video signal via the thin film transistor; and a counter electrode provided in the pixel region and supplied with a reference signal via a counter voltage signal line, the reference signal being a reference for the video signal.

Abstract: A gateway apparatus includes a sorting destination storing unit which stores information of a sorting destination that performs a process according to a destination, a sorting unit which outputs an input destination and transmission data to a sorting destination according to the destination searched from information stored in the sorting destination storing unit, a transmission destination storing unit which stores information of a transmission destination for each destination, an input/output unit which performs a transmission process and a reception process according to a corresponding protocol stack, and a protocol converting unit which assembles, when a destination and transmission data are input from the sorting unit, the destination and the transmission data as data that matches a format of a corresponding protocol stack, and instructs the input/output unit of a corresponding protocol stack to transmit the assembled data to a transmission destination according to the destination.

Abstract: A liquid crystal display device is provided with: a number of gate signal lines and a number of drain signal lines formed so as to cross the gate signal lines provided on the surface of one of a pair of substrates provided so as to face each other with liquid crystal in between on the liquid crystal side; and thin film transistors connected to a gate signal line and a drain signal line, pixel electrodes to which a video signal is supplied from a drain signal line via a thin film transistor, and a counter electrode to which a reference signal which becomes a reference for the video signal is supplied via a counter voltage signal line provided in pixel regions surrounded by a pair of adjacent gate signal lines and a pair of adjacent drain signal lines, and is characterized in that the above described counter electrodes are formed of a transparent conductive film, the above described pixel electrodes are formed of a transparent conductive film and on the liquid crystal side relative to the above described counte

Abstract: A method and an apparatus for enabling a data signal to be transmitted stably at high speed over long distances without using thicker cables and without increasing physical quantities of such resources as transmitting-receiving circuit elements are disclosed. On the transmitting side, the phase of a clock signal relative to the data signal is modified in accordance with the distance between the transmitting and the receiving sides, the clock signal being transmitted along with the data signal. On the receiving side, the incoming data signal is received in synchronism with the received clock signal.

Abstract: In an electronic device comprising a first substrate having at least one first electronic circuit element thereon, a second substrate having at least one second electronic circuit element thereon, a substrate connector through which the first and second electronic circuit elements are connected electrically to each other, and an electrically grounded chassis receiving the first and second substrates, the first substrate has thereon a first electromagnetic shielding plate including an electrically conductive material, the second substrate has thereon a second electromagnetic shielding plate including the electrically conductive material, the first and second electromagnetic shielding plates are electrically connected to the chassis, and a wire length between a wire length limited electronic circuit element on the first substrate and another of the electronic circuit elements on the second substrate is limited for ensuring a high speed responsive operation therebetween.

Abstract: A variable delay circuit including delay devices each having a plurality of delay units connected successively, only some of the delay units of the delay devices being connected to a signal transmission line, wherein a delay time is controlled by activating or inactivating the plurality of delay units according to control signals applied to control input terminals provided respectively for said plurality of delay units.

Abstract: The invention relates to method and apparatus for adjusting a clock signal which is supplied to an electronic apparatus. After the turn-on of a power source of the electronic apparatus, it is detected that a temperature of at least a part of devices in the electronic apparatus substantially reaches a saturation state. When the temperature of the device reaches the saturation state, a phase adjustment of the clock signal of the electronic apparatus is executed. After completion of the phase adjustment of the clock signal, its adjusting state is fixed.

Abstract: The present invention provides a clock signal supply method and system. A reference signal and a synchronizing signal are generated, as well as a clock signal, at a clock signal generating source end. Both the reference signal and the synchronizing signal have a period longer than that of the clock signal. The clock signal at a clock signal destination end is frequency divided in synchronism with the synchronizing signal to provide a sample to be compared with the reference signal. The resultant frequency-divided signal is compared with the reference signal in phase. A delay control is made for the clock signal in accordance with the result of the comparison to adjust the phase of the clock signal at the signal destinations.

Abstract: The present invention relates to a clock signal supplying device provided with an automatic phase regulating function for preventing errors in the phase regulation due to noise. In the device according to the present invention, there is disposed a reference signal serving as a phase reference, and transmission lines for clock signals and a transmission line for the reference signal are disposed from a clock signal supplying source to devices which are destinations of the distribution of clock signals. The transmission line for the reference signal is adjusted in advance so as to produce no skew. In the device, which is the destination of distribution of the clock signal, there is disposed a variable delay circuit for regulation of the phase of the clock signal and a phase comparing circuit for comparing the output of the variable delay circuit with the phase of the reference signal to output the result of the comparison.

Abstract: A system for feeding clock signals to a plurality of load units comprises an oscillator for generating a first clock signal having a predetermined frequency, a plurality of signal lines for transmitting a signal representative of the first clock signal to a plurality of load units, and delays assigned to the plurality of signal lines for adjusting phases of the signal transmitted on a corresponding line at connection points between the oscillator and the load unit. Each load unit is responsive to the signal transmitted on a corresponding signal line for producing second clock signals with a frequency n times greater than that of the second clock signals where n is an integer greater than one. Each load unit further is responsive to the second clock signal for generating a plurality of third clock signals which have discrete phases. The plurality of load units are synchronized with at least one of the plurality of third clock signals.

Abstract: An ordinary differential type gate circuit has two transistors to which complementary inputs are given and which are turned on and off, and complementary type outputs in accordance with the states of the complementary inputs are generated from the collectors of those transistors. In this invention, there are further added a fixed threshold type gate circuit to which is inputted a control signal and a circuit which, when the control signal is inputted to this fixed threshold type gate circuit, generates complementary outputs in constant states irrespective of the states of the complementary inputs in response to the state of the control signal, thereby preventing the inputs applied to the differential type gate circuit from being reflected to the outputs.

Abstract: A small-sized light-weight resistance reflow soldering apparatus for modifying the wiring pattern on a printed circuit board, with the soldering apparatus including a heating device with an adjustable weight, a supporting mechanism for a vertically movably supporting the heating device, a welding power supply for making the heating device produce heat enough to melt the solder for a predetermined time length, and a case accomodating these constituents. The soldering is effected by the heating device which produces the heat while being pressed against the jointing surface.