Patents by Inventor Seiichi Miyazaki

Seiichi Miyazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7268047
    Abstract: A gate insulating film on a silicon substrate of includes a SiO2 film and a high-k film. The high-k film contains a transition metal, aluminum, silicon, and oxygen. The concentration of silicon in the high-k film is higher than the concentrations of the transition metal and aluminum in the vicinity of the interface with the SiO2 film and the vicinity of the interface with the gate electrode. Furthermore, it is preferable that the concentration of silicon is the highest at least in one of the vicinity of the interface with the SiO2 film or the vicinity of the interface with the gate electrode, gradually decreases with distance from these interfaces, and becomes the lowest in a central part of the high-k film.
    Type: Grant
    Filed: February 21, 2006
    Date of Patent: September 11, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsunetoshi Arikado, Takaaki Kawahara, Kazuyoshi Torii, Hiroshi Kitajima, Seiichi Miyazaki
  • Patent number: 7250368
    Abstract: The present invention provides a method for manufacturing a semiconductor wafer capable of manufacturing a wafer without ring-like sag in an outer peripheral portion thereof when polishing an alkali etched wafer, and a wafer without the ring-like sag in an outer peripheral portion thereof. The present invention comprises: a back surface part polishing and edge polishing step for performing back surface part polishing and edge polishing such that mirror polishing is performed on a chamfered portion and an inner part extending inward from a boundary between the chamfered portion and a back surface of a starting wafer; and a front surface polishing step for mirror polishing a front surface of the wafer subjected to the back surface part polishing and edge polishing step holding the wafer by the back surface thereof.
    Type: Grant
    Filed: April 24, 2003
    Date of Patent: July 31, 2007
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Takahiro Kida, Seiichi Miyazaki, Kazuhiko Nishimura, Nobuyuki Hayashi, Katsunori Arai
  • Publication number: 20060138572
    Abstract: A gate insulating film on a silicon substrate of includes a SiO2 film and a high-k film. The high-k film contains a transition metal, aluminum, silicon, and oxygen. The concentration of silicon in the high-k film is higher than the concentrations of the transition metal and aluminum in the vicinity of the interface with the SiO2 film and the vicinity of the interface with the gate electrode. Furthermore, it is preferable that the concentration of silicon is the highest at least in one of the vicinity of the interface with the SiO2 film or the vicinity of the interface with the gate electrode, gradually decreases with distance from these interfaces, and becomes the lowest in a central part of the high-k film.
    Type: Application
    Filed: February 21, 2006
    Publication date: June 29, 2006
    Inventors: Tsunetoshi Arikado, Takaaki Kawahara, Kazuyoshi Torii, Hiroshi Kitajima, Seiichi Miyazaki
  • Patent number: 7034369
    Abstract: A gate insulating film on a silicon substrate includes a SiO2 film and a high-k film. The high-k film contains a transition metal, aluminum, silicon, and oxygen. The concentration of silicon in the high-k film is higher than the concentrations of the transition metal and aluminum in the vicinity of the interface with the SiO2 film and the vicinity of the interface with the gate electrode. Furthermore, it is preferable that the concentration of silicon is the highest at least in one of the vicinity of the interface with the SiO2 film or the vicinity of the interface with the gate electrode, gradually decreases with distance from these interfaces, and becomes the lowest in a central part of the high-k film.
    Type: Grant
    Filed: August 9, 2004
    Date of Patent: April 25, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsunetoshi Arikado, Takaaki Kawahara, Kazuyoshi Torii, Hiroshi Kitajima, Seiichi Miyazaki
  • Publication number: 20050142882
    Abstract: The present invention provides a method for manufacturing a semiconductor wafer capable of manufacturing a wafer without ring-like sag in an outer peripheral portion thereof when polishing an alkali etched wafer, and a wafer without the ring-like sag in an outer peripheral portion thereof. The present invention comprises: a back surface part polishing and edge polishing step for performing back surface part polishing and edge polishing such that mirror polishing is performed on a chamfered portion and an inner part extending inward from a boundary between the chamfered portion and a back surface of a starting wafer; and a front surface polishing step for mirror polishing a front surface of the wafer subjected to the back surface part polishing and edge polishing step holding the wafer by the back surface thereof.
    Type: Application
    Filed: April 24, 2003
    Publication date: June 30, 2005
    Inventors: Takahiro Kida, Seiichi Miyazaki, Kazuhiko Nishimura, Nobuyuki Hayashi, Katsunori Arai
  • Publication number: 20050045970
    Abstract: A gate insulating film on a silicon substrate includes a SiO2 film and a high-k film. The high-k film contains a transition metal, aluminum, silicon, and oxygen. The concentration of silicon in the high-k film is higher than the concentrations of the transition metal and aluminum in the vicinity of the interface with the SiO2 film and the vicinity of the interface with the gate electrode. Furthermore, it is preferable that the concentration of silicon is the highest at least in one of the vicinity of the interface with the SiO2 film or the vicinity of the interface with the gate electrode, gradually decreases with distance from these interfaces, and becomes the lowest in a central part of the high-k film.
    Type: Application
    Filed: August 9, 2004
    Publication date: March 3, 2005
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventors: Tsunetoshi Arikado, Takaaki Kawahara, Kazuyoshi Torii, Hiroshi Kitajima, Seiichi Miyazaki
  • Patent number: 6844269
    Abstract: An etchant and an etching method that contribute to prevention of metal contamination of a semiconductor silicon wafer, and a semiconductor silicon wafer in which metal contamination is extremely reduced, are provided. The etchant according to the present invention is prepared by immersing stainless steel in an alkali aqueous solution for not less than 10 hours. In the etching method according to the present invention, a semiconductor silicon wafer is etched by using the etchant. Thereby, the semiconductor silicon wafer according to the present invention, in which metal contamination is extremely reduced, is obtained.
    Type: Grant
    Filed: December 25, 2000
    Date of Patent: January 18, 2005
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventor: Seiichi Miyazaki
  • Publication number: 20040072437
    Abstract: The present invention relates to a method for producing a silicon wafer, wherein the method comprises at least a lapping process by use of loose abrasive grains and an etching process by use of an alkaline etching solution, lapping is performed in the lapping process by use of abrasive grains having a maximum grain diameter of 21 &mgr;m or less and an average grain diameter of 8.5 &mgr;m or less serving as the loose abrasive grains, and after that, etching is performed in the etching process by use of an alkaline solution having a concentration of an alkaline component of 50% by weight or more serving as the alkaline etching solution, and relates to a silicon wafer produced by the production method. Thus, there can be provided a method for producing a silicon wafer which can prevent degradation of surface roughness of the wafer and flatness of the whole wafer, and a silicon wafer produced by the method.
    Type: Application
    Filed: July 31, 2003
    Publication date: April 15, 2004
    Inventors: Naoto Iizuka, Takashi Nihonmatsu, Masahiko Yoshida, Seiichi Miyazaki
  • Publication number: 20030008504
    Abstract: An etchant and an etching method that contribute to prevention of metal contamination of a semiconductor silicon wafer, and a semiconductor silicon wafer in which metal contamination is extremely reduced, are provided. The etchant according to the present invention is prepared by immersing stainless steel in an alkali aqueous solution for not less than 10 hours. In the etching method according to the present invention, a semiconductor silicon wafer is etched by using the etchant. Thereby, the semiconductor silicon wafer according to the present invention, in which metal contamination is extremely reduced, is obtained.
    Type: Application
    Filed: August 13, 2001
    Publication date: January 9, 2003
    Inventor: Seiichi Miyazaki
  • Patent number: 6432837
    Abstract: A method of processing a semiconductor wafer sliced from a monocrystalline ingot comprises at least the steps of chamfering, lapping, etching, mirror-polishing, and cleaning. In the etching step, alkali etching is first performed and then acid etching, preferably reaction-controlled acid etching, is performed. The etching amount of the alkali etching is greater than the etching amount of the acid etching. Alternatively, in the etching step, reaction-controlled acid etching is first performed and then diffusion-controlled acid etching is performed. The etching amount of the reaction-controlled acid etching is greater than the etching amount of the diffusion-controlled acid etching.
    Type: Grant
    Filed: February 7, 2001
    Date of Patent: August 13, 2002
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Takashi Nihonmatsu, Seiichi Miyazaki, Masahiko Yoshida, Hideo Kudo, Tadahiro Kato
  • Patent number: 6346485
    Abstract: A method of processing a semiconductor wafer sliced from a monocrystalline ingot comprises at least the steps of chamfering, lapping, etching, mirror-polishing, and cleaning. In the etching step, alkali etching is first performed and then acid etching, preferably reaction-controlled acid etching, is performed. The etching amount of the alkali etching is greater than the etching amount of the acid etching. Alternatively, in the etching step, reaction-controlled acid etching is first performed and then diffusion-controlled acid etching is performed. The etching amount of the reaction-controlled acid etching is greater than the etching amount of the diffusion-controlled acid etching.
    Type: Grant
    Filed: August 7, 2000
    Date of Patent: February 12, 2002
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Takashi Nihonmatsu, Seiichi Miyazaki, Masahiko Yoshida, Hideo Kudo, Tadahiro Kato
  • Publication number: 20010008807
    Abstract: A method of processing a semiconductor wafer sliced from a monocrystalline ingot comprises at least the steps of chamfering, lapping, etching, mirror-polishing, and cleaning. In the etching step, alkali etching is first performed and then acid etching, preferably reaction-controlled acid etching, is performed. The etching amount of the alkali etching is greater than the etching amount of the acid etching. Alternatively, in the etching step, reaction-controlled acid etching is first performed and then diffusion-controlled acid etching is performed. The etching amount of the reaction-controlled acid etching is greater than the etching amount of the diffusion-controlled acid etching.
    Type: Application
    Filed: February 7, 2001
    Publication date: July 19, 2001
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Takashi Nihonmatsu, Seiichi Miyazaki, Masahiko Yoshida, Hideo Kudo
  • Patent number: 6239039
    Abstract: A method of processing a semiconductor wafer sliced from a monocrystalline ingot comprises at least the steps of chamfering, lapping, etching, mirror-polishing, and cleaning. In the etching step, alkali etching is first performed and then acid etching, preferably reaction-controlled acid etching, is performed. The etching amount of the alkali etching is greater than the etching amount of the acid etching. Alternatively, in the etching step, reaction-controlled acid etching is first performed and then diffusion-controlled acid etching is performed. The etching amount of the reaction-controlled acid etching is greater than the etching amount of the diffusion-controlled acid etching.
    Type: Grant
    Filed: December 8, 1998
    Date of Patent: May 29, 2001
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Takashi Nihonmatsu, Seiichi Miyazaki, Masahiko Yoshida, Hideo Kudo, Tadahiro Kato
  • Patent number: 5976983
    Abstract: There is disclosed a method of cleaning a semiconductor wafer after lapping in the manufacture thereof comprising the steps of slicing a monocrystalline ingot into a semiconductor wafer, and chamfering, lapping, acid-etching, and then mirror-polishing the thus-obtained semiconductor wafer. The semiconductor wafer is cleaned in a strong-alkaline aqueous solution at a point of time after the lapping and before the acid-etching, such that the surface of the semiconductor wafer is dissolved in an amount in the range of 4-8 .mu.m. The cleaning method prevents generation of a protrusion on the outer circumferential end portion of the wafer in the subsequent acid-etching step.
    Type: Grant
    Filed: February 9, 1998
    Date of Patent: November 2, 1999
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Seiichi Miyazaki, Sumiyoshi Okada
  • Patent number: 5784373
    Abstract: A switching device for LAN is provided for switching packets in ETHERNET. The switching device includes an arrangement for storing the packet received at one of a plurality of receiving ports respectively connected to ETHERNET segments in a receiving buffer commonly used by the whole of the device, by means of a storage device of the receiving buffer. A transmitting destination port for the packet is determined through the use of an address filter device also common for the whole device. A transmitting buffer includes a storage device which receives the packet from the receiving buffer. Then, the packet is transferred from the storage device of the transmitting buffer to one of a plurality of transmitting ports corresponding to the determined address.
    Type: Grant
    Filed: February 20, 1996
    Date of Patent: July 21, 1998
    Assignee: Matsushita Electric Works, Ltd.
    Inventors: Tadashi Satake, Seiichi Miyazaki, Mario Cardona
  • Patent number: 4255813
    Abstract: A dicode transmission system wherein a data is transmitted with the aid of an intermittent asynchronous system in the form of dicode signal. The disclosed system delivers a reset pulse from a transmitter side prior to the starting of a text transmission.
    Type: Grant
    Filed: November 17, 1978
    Date of Patent: March 10, 1981
    Assignee: Ohkura Electric Co., Ltd.
    Inventor: Seiichi Miyazaki
  • Patent number: 4153848
    Abstract: A receiver circuit for receiving a double current pulse signal from a transmission line and delivering positive pulse or a negative pulse corresponding to that of the double current pulse signal in a discriminating manner. The circuit comprises an input transformer having a secondary winding divided into two halves; a resistor connected in series with each output terminal of the input transformer and having a resistance value which is considerably higher than a characteristic impedance of the transmission line; a diode having a cathode connected to an output terminal of the resistor and an anode connected to ground; and an amplifier having input terminals connected to the resistor and the diode, respectively, and delivering either a positive pulse or a negative pulse corresponding to that of the double current pulse signal in a discriminating manner.
    Type: Grant
    Filed: July 6, 1977
    Date of Patent: May 8, 1979
    Assignee: Ohkura Electric Co. Ltd.
    Inventor: Seiichi Miyazaki
  • Patent number: 4121118
    Abstract: A bipolar signal generating apparatus for generating a bipolar signal having positive and negative polarities and comprising a switch means for connecting two terminals of a primary winding of a transformer with each other when the bipolar signal has a level of its neutral region.
    Type: Grant
    Filed: July 6, 1977
    Date of Patent: October 17, 1978
    Assignee: Ohkura Electric Co., Ltd.
    Inventor: Seiichi Miyazaki
  • Patent number: 4078228
    Abstract: A plurality of data stations are connected in series by a "transmission line" to form a loop data communication system through which signals are transmitted unidirectionally. The transmission of the data is effected by using an information block containing two frames A and B as one unit. A central data station among the plurality of data stations is constructed to retransmit the received contents of frame A by frame B. The transmitting data station transmits the information by inserting it in frame A and an addressed data station receives the content of frame B.
    Type: Grant
    Filed: March 16, 1976
    Date of Patent: March 7, 1978
    Assignee: Ohkura Electric Co., Ltd.
    Inventor: Seiichi Miyazaki