Abstract: A semiconductor chip of the present invention is provided with a switching means which connects a first signal terminal to a first internal signal wiring in response to a control terminal being in a first state, connects the first signal terminal to a second internal signal wiring different from the first internal signal wiring in response to the control terminal being in a second state different from the first state, and connects a second signal terminal to the first internal signal wiring. Since it is possible to switch the function of the first signal terminal and the function of the second signal terminal, wiring within a package is facilitated.

Abstract: A decode circuit for use in a semiconductor memory device can prevent an increase of an area of X-decoder and can possess a plurality of banks with operating speed maintained. A word line selection signal makes a word line of a first bank region high level, before it makes first bank selection measure "off" to separate word line selection measure from the first bank region. Next, it makes second bank selection measure "on" to use the word line selection measure for selecting the word line of the second bank region so that one word line selection measure is used in common in terms of both the first bank region and the second bank region.

Abstract: A static random access memory device in which a time required for testing memory cells Is shortened. The static random access memory device includes a test mode setting circuit for activating, in a test mode, a plurality of write circuits and a plurality of sense amplifiers. The device also includes a test mode switching circuit. An input data from an input circuit is written in the plurality of memory cells simultaneously through the write circuits. A plurality of data read out from the memory cells simultaneously are transferred to the test mode switching circuit which decides coincidence among the read data. On the basis of the decision result, an output circuit outputs at a data output terminal output signals in three states, that is, in a logic "1", a logic "0" or a high impedance. Since the plurality of memory cells are checked simultaneously, the required time for testing the memory cells can be shortened.

Abstract: A semiconductor memory device with a redundant memory cell array includes two transfer gate circuits. The first transfer gate circuit transfers a signal selected from two signals, one of which from a first detecting circuit for detecting a selection of a redundant memory cell array to substitute an ordinary memory cell which includes a faulty memory cell, the other from a second detecting circuit for detecting an address of the ordinary memory cell array including the faulty memory cell. The second transfer gate circuit transfers a signal transferred from the first transfer gate circuit when the semiconductor memory device is not in a write enable state. When the semiconductor memory device is not in a write enable state, it is possible to detect a selection of the redundant memory cell array or an address of the ordinary memory cell array including the faulty memory cell, by monitoring the state of an output terminal of the semiconductor memory cell.

Abstract: In a semiconductor memory device with a redundant memory cell array provided in association with a memory cell array partially replacable with the redundant memory cells, each programming circuit has a conduction path flowing a current in the absence of a defective memory cell for shifting a redundant memory controller into an inactive state, a redundant memory activation circuit produces an enable signal in the presence of the detective memory cell for shifting the controller into an active state and further produces a disenable signal in the absence of the defective memory cell, and a blocking transistor is provided in the conduction path and responsive to the disenable signal to block the conduction path, thereby causing the amount of current consumed to be decreased.