Patents by Inventor Seiichi Natkatani

Seiichi Natkatani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Package equipped with semiconductor chip and method for producing same
    Patent number: 7649267
    Abstract: A highly reliable, high-productivity package equipped with a semiconductor chip, and a method for producing the same. In a package (100) comprising a semiconductor chip (10) and a mounting substrate (30), a plurality of electrode terminals (12) are formed on the surface (10a) of the semiconductor chip (10) opposing the mounting substrate side, connection terminals (32) respectively corresponding to the plurality of electrode terminals (12), are formed on the mounting substrate (30), the connection terminals (32) on the mounting substrate (30) and the electrode terminals (12) are electrically connected collectively by solder bumps (17) formed in self-assembly, an electrode pattern (20) not connected with the electrode terminals (12) and the connection terminals (32) is formed on the chip surface (10a) or the surface (35) of the mounting substrate (30) corresponding to the chip surface (10a), and solder (19) is accumulated on the electrode pattern (20).
    Type: Grant
    Filed: March 8, 2006
    Date of Patent: January 19, 2010
    Assignee: Panasonic Corporation
    Inventors: Tsukasa Shiraishi, Yukihiro Ishimaru, Seiji Karashima, Seiichi Natkatani, Hiroki Yabe
  • Package Equipped with Semiconductor Chip and Method for Producing Same
    Publication number: 20080265437
    Abstract: A highly reliable, high-productivity package equipped with a semiconductor chip, and a method for producing the same. In a package (100) comprising a semiconductor chip (10) and a mounting substrate (30), a plurality of electrode terminals (12) are formed on the surface (10a) of the semiconductor chip (10) opposing the mounting substrate side, connection terminals (32) respectively corresponding to the plurality of electrode terminals (12), are formed on the mounting substrate (30), the connection terminals (32) on the mounting substrate (30) and the electrode terminals (12) are electrically connected collectively by solder bumps (17) formed in self-assembly, an electrode pattern (20) not connected with the electrode terminals (12) and the connection terminals (32) is formed on the chip surface (10a) or the surface (35) of the mounting substrate (30) corresponding to the chip surface (10a), and solder (19) is accumulated on the electrode pattern (20).
    Type: Application
    Filed: March 8, 2006
    Publication date: October 30, 2008
    Inventors: Tsukasa Shiraishi, Yukihiro Ishimaru, Seiji Karashima, Seiichi Natkatani, Hiroki Yabe