Abstract: A QAM modulation system capable of setting a number of multilevel to approximate 2(p+0.25) (p is an integer equal to or more than 3) or 2(p+q/n). An input data signal of 4p+1 bits are converted into four signals of p+1 bits, there being a predetermined relationship between the input data signal and the converted signals. The converted four signals are assigned to four phase planes, respectively. The four signals are time-division multiplexed and multilevel-modulated. Thereby, it becomes possible to set the number of multilevel to approximate 2(p+0.25).

Abstract: In a phase modulation apparatus for modulating a phase of a carrier signal by an input signal to produce a phase-shift-keying-modulated wave, a data converter converts an input data signal having 3 bits long as the input signal into first and second ternary converted data signals. A ternary phase shift keying modulator modulates, in synchronism with a clock signal, the phase of the carrier signal by the first and the second ternary converted data signals to produce, as the phase-shift-keying-modulated wave, first and second ternary phase shift keying modulated signals, respectively. Disposed between the data converter and the ternary phase shift keying modulator, a parallel-serial converter temporally multiplexes the first and the second ternary converted data signals into first and second multiplexed signals, respectively.

Abstract: A scraper conveyor has a machine frame consisting of a horizontal grains supply case, a horizontal discharge case placed at a position higher than the supply case and having a discharge port, and a slanted case arranged between both these cases; a pair of sprockets arranged at both the ends of the machine frame; an endless chain provided with a number of paired scrapers for conveying grains and extending around the sprockets; a curved guide rail extending along substantially the whole length of the machine frame and being arranged in the frame in order to support upward the upper returning chain portion of the chain; a pair of chain sustaining members for preventing the upper returning chain portion and lower advancing chain portion of the chain from floating; and chain support members for supporting upward the lower advancing chain portion.

Abstract: In order to produce first and second Lee-error correcting code sequences in a multilevel quadrature amplitude modulator comprising a code converting unit (10) for converting first and second 2.sup.m -level input digital signals into first and second major converted signals by rearranging a square signal point arrangement into an approximately circular arrangement on a phase plane, each of the first and the second major converted signals consisting of m binary bits numbered from a first (least significant) bit through an m-th (most significant) bit, a first error correcting code producing circuit (21) carries out error correcting calculation for the first through an n-th bits of the first major converted signal to produce the first Lee-error correcting code sequence where n represents an integer which is not less than two and is not less than m. Similarly, a second error correcting code producing circuit (22) produces the second Lee-error correcting code sequence.

Abstract: In an encoder for use in encoding each input signal unit of N bits into each of error correcting codewords, each input signal unit is grouped into a plurality of parts which have bit lengths N1 and N2 in consideration of a transmission rate on a transmission path and which are individually encoded into partial encoded codewords which individually include redundancy signals, respectively. The partial encoded codewords may have different error correction ability and different code lengths. The partial encoded codewords are combined together into each of the error correcting codeword which may be transmitted to the transmission path at a transmission rate close to an allowable transmission rate of the transmission path. A decoder decodes each error correcting codeword into each of output signal units by dividing each error correcting codeword into divided codewords and by individually decoding the divided codewords.

Abstract: An equalizer is provided with a branching device for branching a digitally modulated signal into two outputs. A series of weighting devices weights one of the outputs of the branching means, and a series of second weighting devices equal to or fewer in number than the first weighting devices weights the remaining output of the branching means. Combining elements equal in number to the first weighting devices combine two or three inputs, and delaying means fewer in number than the combining elements are interconnected with the combining elements in a sequential, alternating manner. The outputs of the first weighting devices are respectively applied to the combining elements while those of the second weighting devices are respectively applied to selected ones of the combining elements. The invention provides a construction where the number of taps of the equalizer may be easily increased without creating the necessity of combining circuits having an increased number of inputs.

Abstract: In a multilevel modulator for use in modulating an input digital signal of N levels into a multilevel modulated signal, the input digital signal is converted by a code converting unit into a major converted signal for the input digital signal and a minor converted signal corresponding to the major converted signal. The major converted signal is rearranged into groups each of which consists of a predetermined number of levels smaller than N and which is produced in a time division fashion together with with minor converted signal. A signal producing unit processes each group to produce a Lee-error correcting code sequence. Alternatively, major and minor converted signals are produced on quadrature-phase amplitude modulation of a circular signal arrangement of N-levels to divide the circular signal arrangement into a square signal arrangement and the remaining signal arrangement. In a counterpart multilevel demodulator, an inverse operation is carried out to reproduce the input digital signal.

Abstract: A digital signal combining circuit for a diversity receiver for digital communication comprises buffer memories (16) for memorizing digital signal sequences produced by receiver units (11, 12), respectively, and an APC loop (26-39) for locking the phases of read-out clocks for simultaneously reading the memories to an averaged phase of the digital signal sequences. No code error appears in an output signal of the receiver provided that the phase difference between two of the digital signal sequences from which the output signal is selected, is less than m bit periods, where m represents the number of memory cells of each buffer memory.