Abstract: A federated learning system in which a plurality of local servers repeatedly learn cooperatively through communications between the plurality of local servers and a central server via a network. The local server includes a decryption unit, a mean gradient calculation unit, a model updating unit, a validation error calculation unit, an encryption unit, and a local transmission unit that transmits at least one of a current local mean gradient and a current local validation error. The central server includes a central reception unit, a model selection unit, a weight determination unit, and a central transmission unit. The central reception unit receives encrypted current local models and at least one of current local training data counts, the current local mean gradients, and the current local validation errors from the plurality of respective local servers.

Abstract: A switching converter with improved load transient response is provided, including a panic comparator with a reset switch, a panic latch that is set by an output of the panic comparator and reset in conjunction with a strobe timing, and a timing generator which generates reset and strobe signals. The timing generator may include a gated oscillator, enabled by the panic latch. The panic comparator may include an HPF element, configured to accelerate the panic comparator response. The switching converter may be multi-phase.

Abstract: A switching converter with improved load transient response is provided, including a panic comparator with a reset switch, a panic latch that is set by an output of the panic comparator and reset in conjunction with a strobe timing, and a timing generator which generates reset and strobe signals. The timing generator may include a gated oscillator, enabled by the panic latch. The panic comparator may include an HPF element, configured to accelerate the panic comparator response. The switching converter may be multi-phase.

Abstract: A solution is provided for a current balance feedback method to improve stability in a multi-phase DC-DC switching converter, where the current balance feedback signal is added to the PWM duty signal, after the PWM comparator. Using this feedback method, current balance oscillation issues caused by the non-linearity of the main control loop can be solved, and provide better current balance stability in the switching converter. Advantages include improving the stability of the current balance feedback loop by introducing the correction post PW modulation in the time domain, effectively bypassing interaction with the PW modulator. The current balance feedback loop stability improvement reduces PCB design effort and iteration.

Abstract: A solution is provided for a current balance feedback method to improve stability in a multi-phase DC-DC switching converter, where the current balance feedback signal is added to the PWM duty signal, after the PWM comparator. Using this feedback method, current balance oscillation issues caused by the non-linearity of the main control loop can be solved, and provide better current balance stability in the switching converter. Advantages include improving the stability of the current balance feedback loop by introducing the correction post PW modulation in the time domain, effectively bypassing interaction with the PW modulator. The current balance feedback loop stability improvement reduces PCB design effort and iteration.

Abstract: A thermometer-coded Digital to Analog Converter (DAC) is described, whose output is changed with fast speed, and reduced output overshoot or undershoot. The thermometer-coded DAC has selection switches and an up/down counter, with DAC codes separated into higher and lower bits. The lower bits increase up to a maximum code, then decrease. The configuration of resistors in the DAC reduces output spike, especially at the DAC code changing point.

Abstract: A thermometer-coded Digital to Analog Converter (DAC) is described, whose output is changed with fast speed, and reduced output overshoot or undershoot. The thermometer-coded DAC has selection switches and an up/down counter, with DAC codes separated into higher and lower bits. The lower bits increase up to a maximum code, then decrease. The configuration of resistors in the DAC reduces output spike, especially at the DAC code changing point.

Abstract: A circuit and method for a switching converter that modifies the clock frequency when the panic comparator is activated is proposed. This solution for a switching converter is achieved by increases in the switching frequency in response to an undershoot condition. In summary, a switching converter circuit, comprising at least one phase functional block configured to provide an output voltage, a panic comparator configured to evaluate voltage excursion conditions of the output voltage, and a clock generator with pulse insertion function wherein the pulse insertion function is configured to increase the switching frequency during a voltage excursion condition to minimize or mitigate voltage excursions. In addition, a switching converter circuit, comprising a clock generator with a pulse width extender configured to provide a signal to said pulse insertion function logic.

Abstract: An object of the disclosure is to provide cancelling of the output voltage deviation in a switching converter, caused by Equivalent Series Inductance (ESL) of the output capacitor, using switching node information. A further object of the disclosure is to eliminate a step-like voltage deviation in the equalized output, further eliminating the need to increase the Panic comparator offset reference, and eliminating the need to reduce the bandwidth of the pulse-width modulation control loop. Still further, another object of the disclosure is to merge some of the new components depending on the circuit topology. Still further, another object of the disclosure is to implement the new components with the same silicon as the control block, for matching the output voltage ripple and the cancelling signal control.

Abstract: A system is disclosed which provides the minimization of peak-to-peak output voltage ripple in multi-phase DC-DC switching converters, with two or more different value inductors (asymmetric inductors), by the optimization of phase-shifting determined by the inductance on each phase. An object of the disclosure is to ensure both the AC accuracy of the output voltage and the efficiency of the DC-DC switching converter is increased. The output voltage ripple improvement is shown to be dependent on the duty-cycle. Another object of the disclosure is to minimize the total inductor current ripple and improving the efficiency of the DC-DC switching converter by reducing the capacitor loss. Still another object of the disclosure is to minimize the output voltage ripple in the multi-phase DC-DC switching converter by ensuring the sum of the inductor current vectors is equal to zero.

Abstract: A system is disclosed which provides the minimization of peak-to-peak output voltage ripple in multi-phase DC-DC switching converters, with two or more different value inductors (asymmetric inductors), by the optimization of phase-shifting determined by the inductance on each phase. An object of the disclosure is to ensure both the AC accuracy of the output voltage and the efficiency of the DC-DC switching converter is increased. The output voltage ripple improvement is shown to be dependent on the duty-cycle. Another object of the disclosure is to minimize the total inductor current ripple and improving the efficiency of the DC-DC switching converter by reducing the capacitor loss. Still another object of the disclosure is to minimize the output voltage ripple in the multi-phase DC-DC switching converter by ensuring the sum of the inductor current vectors is equal to zero.

Abstract: A circuit and method for providing an improved current monitoring circuit for a switching regulator. A circuit providing switching regulation with an improved current monitor, comprising a pulse width modulation (PWM) controller configured to provide P- and N-drive signals, an output stage connected to said PWM controller and configured to provide switching, comprising a high-side and low-side transistor, driven by said P- and N-drive signals, respectively, a sense circuit configured to provide output current sensing from the output stage during a sampling period when the N-drive signal is active, and a sampling timing generator configured to provide a an n-sampling signal, nsample, to the sense circuit, wherein a start of the n-sampling signal is delayed by a first delay after the sampling period and the n-sampling signal is ended prior to an end of the sampling period by a second delay.

Abstract: A current monitoring circuit capable of being integrated onto an integrated circuit chip with the current source to be monitored, wherein the monitored current is digitized to be transmitted within and external to the host integrated circuit chip. The current monitoring circuit was originally conceived to monitor output current of a buck switching regulator but can be used in other applications. A replica transistor is drain connected to a replicated transistor, wherein an operational transconductor controls the replica transistor to produce the same current that flows in the replicated transistor and connects a copy of the current of the replicated transistor current to an integrating type ADC.

Abstract: A circuit and method for a switching converter that modifies the clock frequency when the panic comparator is activated is proposed. This solution for a switching converter is achieved by increases in the switching frequency in response to an undershoot condition. In summary, a switching converter circuit, comprising at least one phase functional block configured to provide an output voltage, a panic comparator configured to evaluate voltage excursion conditions of the output voltage, and a clock generator with pulse insertion function wherein the pulse insertion function is configured to increase the switching frequency during a voltage excursion condition to minimize or mitigate voltage excursions. In addition, a switching converter circuit, comprising a clock generator with a pulse width extender configured to provide a signal to said pulse insertion function logic.

Abstract: Circuits and methods control output voltage overshoot and undershoot of an SMPC in response to a load current transient. The SMPC control stage has at least one load variation detector that compares a feedback signal with at least one transient threshold level to determine that occurrence of the load current transient. When the load current transient has occurred, the at least one load variation detector causes a switch stage to be turned on to source or sink current to or from the load circuit to compensate the load current transient. A slope detector determines a change in polarity of the slope of the load current transient. When the slope changes polarity, the slope detector sends a signal for preventing an overshoot or an undershoot of the output voltage of the SMPC once the load current transient has been compensated.

Abstract: A multi-phase switched-mode converter has a control circuit configured to receive a shed threshold signal indicating that the total output current has fallen below a total current threshold level. The control circuit further includes slave phase shedding switches that have a common switching pole connected to a current share amplifier of each slave power stage, a first select pole is connected to a phase target current level, and a second select pole is connected to a phase zero target current level. A control terminal is connects the phase zero target current signal to each slave power stage to decreases their output currents to approximately a zero level. When the output current approaches the zero level, the slave power stages are deactivated. A panic circuit activates the slave power stages when the load current increases precipitously.

Abstract: A multi-phase switched-mode converter has a control circuit configured to receive a shed threshold signal indicating that the total output current has fallen below a total current threshold level. The control circuit further includes slave phase shedding switches that have a common switching pole connected to a current share amplifier of each slave power stage, a first select pole is connected to a phase target current level, and a second select pole is connected to a phase zero target current level. A control terminal is connects the phase zero target current signal to each slave power stage to decreases their output currents to approximately a zero level. When the output current approaches the zero level, the slave power stages are deactivated. A panic circuit activates the slave power stages when the load current increases precipitously.

Abstract: A circuit and method for providing an improved current monitoring circuit for a switching regulator. A circuit providing switching regulation with an improved current monitor, comprising a pulse width modulation (PWM) controller configured to provide P- and N-drive signals, an output stage connected to said PWM controller and configured to provide switching, comprising a high-side and low-side transistor, driven by said P- and N-drive signals, respectively, a sense circuit configured to provide output current sensing from the output stage during a sampling period when the N-drive signal is active, and a sampling timing generator configured to provide a an n-sampling signal, nsample, to the sense circuit, wherein a start of the n-sampling signal is delayed by a first delay after the sampling period and the n-sampling signal is ended prior to an end of the sampling period by a second delay.

Abstract: Reception devices 201 to 20N are arranged one-dimensionally in this order. The reception device 20n has a data input buffer 21, a first clock input buffer 221, and a first clock output buffer 231. The first clock input buffer 221 buffers a clock input to the first clock terminals P21 and P22, and outputs it to the first clock output buffer 231. The first clock output buffer 231 buffers a clock input from the first clock input buffer 221 and outputs it from the second clock terminals P31 and P32. The data input terminals P11 and P12 are located between the first clock terminal and the second clock terminal.

Abstract: A circuit and method for providing switching regulation with an improved current monitor comprising a pulse width modulation (PWM) controller configured to provide an output signal voltage, an output stage configured to provide switching comprising a first and second transistor, and first inverter, a sense circuit configured to provide signal sensing from said output stage, a sampling switch circuit configured to provide sample signals from said sense circuit, a differential integrator circuit configured to provide sample signals from said sampling switch circuit, a comparator configured to provide signals from said integrator circuit, a control logic circuit configured to provide signals from said comparator, a current digital-to-analog converter (DAC) configured to provide feedback signal from said control logic circuit, and, a digital filter configured to provide output current information.