Patents by Inventor Seiichi Sakura

Seiichi Sakura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6359668
    Abstract: A retardation film 30 and an upper polarized light separator 20 are provided on the upper side of a liquid crystal cell 10. A diffuser 40, a lower polarized light separator 50, a color filter 60, a PET film 70 and an Al deposited film 80 are provided on the lower side of the liquid crystal cell 10. As the upper polarized light separator 20 and the lower polarized light separator 50, a polarized light separator (reflective polarizer) is used, which reflects linearly-polarized light in one direction as linearly-polarized light in the one direction, and transmits linearly-polarized light in another direction perpendicular to the one direction as linearly-polarized light in the other direction. The light emitted from LED 120 is introduced into a light guide plate 130 between the upper polarized light separator 20 and the retardation film 30 through a light guide 110. Then the light is emitted from the lower side of the light guide plate 130 to the liquid crystal cell 10.
    Type: Grant
    Filed: January 13, 1999
    Date of Patent: March 19, 2002
    Assignee: Seiko Epson Corporation
    Inventors: Chiyoaki Iijima, Seiichi Sakura, Toshihiko Tsuchihashi
  • Patent number: 6128063
    Abstract: A liquid crystal display apparatus is provided which requires a small, thin and compact area for mounting semiconductor chips for driving liquid crystal and, accordingly, has a reduced cost. Semiconductor chips for driving liquid crystal are mounted on a surface (for example, a first layer) of a multi-layer substrate. The surface has input lines to the chips and output lines from the chips. The input lines have lands for connecting adjacent multi-layer substrates to each other. At least one intermediate layer is formed between an upper layer and a lower layer, the intermediate layer having bus lines. The bus lines and the input lines of the first layer are connected to one another via through holes in the first layer. The output lines of the first layer and terminals of the third layer are connected to one another via through holes in the first, second and third layers.
    Type: Grant
    Filed: June 27, 1997
    Date of Patent: October 3, 2000
    Assignee: Seiko Epson Corporation
    Inventors: Kenji Uchiyama, Eiji Muramatsu, Masaru Kamimura, Shigetoshi Yamada, Kenichi Maruyama, Seiichi Sakura, Kazuaki Furuichi, Kinichi Maeda
  • Patent number: 5986342
    Abstract: A liquid crystal display apparatus is provided which requires a small, thin and compact area for mounting semiconductor chips for driving liquid crystal and, accordingly, has a reduced cost. Semiconductor chips for driving liquid crystal are mounted on a surface (for example, a first layer) of a multi-layer substrate. The surface has input lines to the chips and output lines from the chips. The input lines have lands for connecting adjacent multi-layer substrates to each other. At least one intermediate layer is formed between an upper layer and a lower layer, the intermediate layer having bus lines. The bus lines and the input lines of the first layer are connected to one another via through holes in the first layer. The output lines of the first layer and terminals of the third layer are connected to one another via through holes in the first, second and third layers.
    Type: Grant
    Filed: June 27, 1997
    Date of Patent: November 16, 1999
    Assignee: Seiko Epson Corporation
    Inventors: Kenji Uchiyama, Eiji Muramatsu, Masaru Kamimura, Shigetoshi Yamada, Kenichi Maruyama, Seiichi Sakura, Kazuaki Furuichi, Kinichi Maeda
  • Patent number: 5737272
    Abstract: A liquid crystal display apparatus is provided which requires a small, thin and compact area for mounting semiconductor chips for driving liquid crystal and, accordingly, has a reduced cost. Semiconductor chips for driving liquid crystal are mounted on a surface (for example, a first layer) of a multi-layer substrate. The surface has input lines to the chips and output lines from the chips. The input lines have lands for connecting adjacent multi-layer substrates to each other. At least one intermediate layer is formed between an upper layer and a lower layer, the intermediate layer having bus lines. The bus lines and the input lines of the first layer are connected to one another via through holes in the first layer. The output lines of the first layer and terminals of the third layer are connected to one another via through holes in the first, second and third layers.
    Type: Grant
    Filed: September 8, 1993
    Date of Patent: April 7, 1998
    Assignee: Seiko Epson Corporation
    Inventors: Kenji Uchiyama, Eiji Muramatsu, Masaru Kamimura, Shigetoshi Yamada, Kenichi Maruyama, Seiichi Sakura, Kazuaki Furuichi, Kinichi Maeda
  • Patent number: 5306664
    Abstract: A bump electrode of an inexpensive and reliable semiconductor device is provided in which a remaining metal wire portion produced during bump electrode formation is eliminated. The remaining metal wire portion made in a bump electrode forming method for a semiconductor device using a wire bonding technique is pressed and reshaped from above with heat or ultrasonic waves so as to apply pressure and heat to the bump electrode by using a stamping tool.
    Type: Grant
    Filed: May 15, 1992
    Date of Patent: April 26, 1994
    Assignee: Seiko Epson Corp.
    Inventor: Seiichi Sakura