Patents by Inventor Seiichi Tobe

Seiichi Tobe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Alignment and cutting of microelectronic substrates
    Publication number: 20080156518
    Abstract: A substrate including plural microelectronic device carriers has metallic alignment elements. The alignment elements desirably are disposed in a predetermined positional relationship to terminals on the carriers. The alignment elements are engaged with a carrier frame and a cutting device is aligned with the carrier frame. The cutting device cuts the carriers so that borders of the carriers are in a precise relationship with the terminals.
    Type: Application
    Filed: January 3, 2007
    Publication date: July 3, 2008
    Applicant: Tessera, Inc.
    Inventors: Kenneth Allen Honer, Christopher Paul Wade, Seiichi Tobe, Chung-Chuan Tseng, Ellis Chau, Kyong-Mo Bang
  • Through-hole pin for laminated circuit substrates and method of insertion thereof
    Patent number: 4562301
    Abstract: A through-hole pin connection for laminated circuit elements and method of connection are presented. The laminated circuit element consists of a plurality of individual circuit elements, each element having a land area about the periphery of the through-hole. The through-hole pin has at least one ridged region located along the direction of insertion into the through-hole. Upon insertion, the pin guides a solder into the land areas and the ridged region effects electrical and mechanical contact between the through-hole pin and each of the land areas of the laminated circuit element.
    Type: Grant
    Filed: February 7, 1984
    Date of Patent: December 31, 1985
    Assignee: Nippon Mektron Ltd.
    Inventors: Eiichi Kameda, Seiichi Tobe