Patents by Inventor Seiichi Tomoi
Seiichi Tomoi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8557633Abstract: A technique that makes it possible to enhance the reliability of a module using PCB as its module substrate is provided. Solder connection of a single-chip component 43, an integrated chip component 44, and a semiconductor chip IC2 by Pb-free solder is carried out by heat treatment at a temperature below 280° C. using a heat block. Solder connection of a semiconductor chip IC1 by high-melting point solder is carried out by heat treatment at a temperature of 280° C. or higher using a hot jet. Thus, the semiconductor chip IC1 can be solder connected to PCB 38 using high-melting point solder without the following troubles: damage to the PCB 38 due to heat, for example, burning of solder resist; and peeling of prepreg from a core material. Therefore, the semiconductor chip IC1 can be mounted over the PCB 38 with high connection strength.Type: GrantFiled: April 5, 2011Date of Patent: October 15, 2013Assignee: Renesas Electronics CorporationInventors: Kunio Shigemura, Kenji Hanada, Masaki Nakanishi, Takafumi Nishita, Masayoshi Shinoda, Seiichi Tomoi
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Publication number: 20110183474Abstract: A technique that makes it possible to enhance the reliability of a module using PCB as its module substrate is provided. Solder connection of a single-chip component 43, an integrated chip component 44, and a semiconductor chip IC2 by Pb-free solder is carried out by heat treatment at a temperature below 280° C. using a heat block. Solder connection of a semiconductor chip IC1 by high-melting point solder is carried out by heat treatment at a temperature of 280° C. or higher using a hot jet. Thus, the semiconductor chip IC1 can be solder connected to PCB 38 using high-melting point solder without the following troubles: damage to the PCB 38 due to heat, for example, burning of solder resist; and peeling of prepreg from a core material. Therefore, the semiconductor chip IC1 can be mounted over the PCB 38 with high connection strength.Type: ApplicationFiled: April 5, 2011Publication date: July 28, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Kunio Shigemura, Kenji Hanada, Masaki Nakanishi, Takafumi Nishita, Masayoshi Shinoda, Seiichi Tomoi
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Patent number: 7656030Abstract: Heating elements different in heat generating timing are laminated in a stacked state, and the heating element close to a wiring substrate is allowed to function as a heat diffusion plate for another heating element.Type: GrantFiled: January 10, 2007Date of Patent: February 2, 2010Assignee: Renesas Technology Corp.Inventors: Yasuo Osone, Kenya Kawano, Chiko Yorita, Yu Hasegawa, Yuji Shirai, Naotaka Tanaka, Seiichi Tomoi, Hiroshi Okabe
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Patent number: 7583163Abstract: A technique capable of integrally forming SMR type acoustic wave filters corresponding to multiple bands on the same chip at low cost is provided. In SMR type acoustic wave filters including multiple bandpass filters corresponding to multiple bands formed over the same die (substrate), acoustic multilayer films are formed without or with a minimum number of masks and piezoelectric thin films having different thicknesses for respective bands are collectively formed. For example, after the acoustic multilayer films (low acoustic impedance layers and high acoustic impedance layers) are formed in a deep groove in a terrace paddy field shape over the die in a maskless manner, the piezoelectric thin films are c-axis-oriented and grown, and are polished by CMP method or the like to be adjusted in a thickness for respective bands, and therefore, the SMR type acoustic wave filters for multiple bands are formed over the same chip.Type: GrantFiled: August 10, 2007Date of Patent: September 1, 2009Assignee: Renesas Technology Corp.Inventors: Yasuo Osone, Chiko Yorita, Yuji Shirai, Seiichi Tomoi
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Patent number: 7554193Abstract: A semiconductor device capable of reducing the thermal resistance in a flip chip packaging structure while achieving both the high radiation performance and manufacturing readiness without increasing the manufacturing cost is provided. In a semiconductor device having a semiconductor circuit for power amplification and a control circuit of the semiconductor circuit laminated on a multilayer circuit board, the semiconductor circuit for power amplification and the control circuit are aligned in parallel on the same semiconductor element, and the semiconductor element is flip-chip connected on the multilayer circuit board. Further, a second semiconductor element mounted in addition to the first semiconductor element and all components and submodules are flip-chip connected. Also, a plurality of bumps are united in order to improve the radiation performance and thermal vias of the multilayer circuit board are formed in second and lower layers of the wiring layers in the multilayer circuit board.Type: GrantFiled: August 16, 2006Date of Patent: June 30, 2009Assignee: Renesas Technology Corp.Inventors: Yasuo Osone, Chiko Yorita, Kenya Kawano, Yu Hasegawa, Yuji Shirai, Seiichi Tomoi, Tsuneo Endou, Satoru Konishi, Hirokazu Nakajima
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Publication number: 20080253100Abstract: A technique that makes it possible to enhance the reliability of a module using PCB as its module substrate is provided. Solder connection of a single-chip component 43, an integrated chip component 44, and a semiconductor chip IC2 by Pb-free solder is carried out by heat treatment at a temperature below 280° C. using a heat block. Solder connection of a semiconductor chip IC1 by high-melting point solder is carried out by heat treatment at a temperature of 280° C. or higher using a hot jet. Thus, the semiconductor chip IC1 can be solder connected to PCB 38 using high-melting point solder without the following troubles: damage to the PCB 38 due to heat, for example, burning of solder resist; and peeling of prepreg from a core material. Therefore, the semiconductor chip IC1 can be mounted over the PCB 38 with high connection strength.Type: ApplicationFiled: June 12, 2008Publication date: October 16, 2008Inventors: Kunio Shigemura, Kenji Hanada, Masaki Nakanishi, Takafumi Nishita, Masayoshi Shinoda, Seiichi Tomoi
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Patent number: 7396701Abstract: A technique that makes it possible to enhance the reliability of a module using PCB as its module substrate is provided. Solder connection of a single-chip component 43, an integrated chip component 44, and a semiconductor chip IC2 by Pb-free solder is carried out by heat treatment at a temperature below 280° C. using a heat block. Solder connection of a semiconductor chip IC1 by high-melting point solder is carried out by heat treatment at a temperature of 280° C. or higher using a hot jet. Thus, the semiconductor chip IC1 can be solder connected to PCB 38 using high-melting point solder without the following troubles: damage to the PCB 38 due to heat, for example, burning of solder resist; and peeling of prepreg from a core material. Therefore, the semiconductor chip IC1 can be mounted over the PCB 38 with high connection strength.Type: GrantFiled: November 18, 2005Date of Patent: July 8, 2008Assignee: Renesas Technology Corp.Inventors: Kunio Shigemura, Kenji Hanada, Masaki Nakanishi, Takafumi Nishita, Masayoshi Shinoda, Seiichi Tomoi
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Publication number: 20080129412Abstract: A technique capable of integrally forming SMR type acoustic wave filters corresponding to multiple bands on the same chip at low cost is provided. In SMR type acoustic wave filters including multiple bandpass filters corresponding to multiple bands formed over the same die (substrate), acoustic multilayer films are formed without or with a minimum number of masks and piezoelectric thin films having different thicknesses for respective bands are collectively formed. For example, after the acoustic multilayer films (low acoustic impedance layers and high acoustic impedance layers) are formed in a deep groove in a terrace paddy field shape over the die in a maskless manner, the piezoelectric thin films are c-axis-oriented and grown, and are polished by CMP method or the like to be adjusted in a thickness for respective bands, and therefore, the SMR type acoustic wave filters for multiple bands are formed over the same chip.Type: ApplicationFiled: August 10, 2007Publication date: June 5, 2008Applicant: Renesas Technology Corp.Inventors: Yasuo Osone, Chiko Yorita, Yuji Shirai, Seiichi Tomoi
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Publication number: 20070176298Abstract: Heating elements different in heat generating timing are laminated in a stacked state, and the heating element close to a wiring substrate is allowed to function as a heat diffusion plate for another heating element.Type: ApplicationFiled: January 10, 2007Publication date: August 2, 2007Applicants: Hitachi, Ltd., Renesas Technology Corp.Inventors: Yasuo Osone, Kenya Kawano, Chiko Yorita, Yu Hasegawa, Yuji Shirai, Naotaka Tanaka, Seiichi Tomoi, Hiroshi Okabe
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Publication number: 20070040255Abstract: A semiconductor device capable of reducing the thermal resistance in a flip chip packaging structure while achieving both the high radiation performance and manufacturing readiness without increasing the manufacturing cost is provided. In a semiconductor device having a semiconductor circuit for power amplification and a control circuit of the semiconductor circuit laminated on a multilayer circuit board, the semiconductor circuit for power amplification and the control circuit are aligned in parallel on the same semiconductor element, and the semiconductor element is flip-chip connected on the multilayer circuit board. Further, a second semiconductor element mounted in addition to the first semiconductor element and all components and submodules are flip-chip connected. Also, a plurality of bumps are united in order to improve the radiation performance and thermal vias of the multilayer circuit board are formed in second and lower layers of the wiring layers in the multilayer circuit board.Type: ApplicationFiled: August 16, 2006Publication date: February 22, 2007Inventors: Yasuo Osone, Chiko Yorita, Kenya Kawano, Yu Hasegawa, Yuji Shirai, Seiichi Tomoi, Tsuneo Endou, Satoru Konishi, Hirokazu Nakajima
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Publication number: 20060110859Abstract: A technique that makes it possible to enhance the reliability of a module using PCB as its module substrate is provided. Solder connection of a single-chip component 43, an integrated chip component 44, and a semiconductor chip IC2 by Pb-free solder is carried out by heat treatment at a temperature below 280° C. using a heat block. Solder connection of a semiconductor chip IC1 by high-melting point solder is carried out by heat treatment at a temperature of 280° C. or higher using a hot jet. Thus, the semiconductor chip IC1 can be solder connected to PCB 38 using high-melting point solder without the following troubles: damage to the PCB 38 due to heat, for example, burning of solder resist; and peeling of prepreg from a core material. Therefore, the semiconductor chip IC1 can be mounted over the PCB 38 with high connection strength.Type: ApplicationFiled: November 18, 2005Publication date: May 25, 2006Inventors: Kunio Shigemura, Kenji Hanada, Masaki Nakanishi, Takafumi Nishita, Masayoshi Shinoda, Seiichi Tomoi
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Patent number: 7015127Abstract: Provided is a semiconductor device comprising a first metal film formed above a semiconductor chip, a ball portion formed over said first metal film and made of a second metal, and an alloy layer of said first metal and said second metal which alloy layer is formed between said first metal film and said ball portion, wherein said alloy layer reaches the bottom of said first metal film, and said ball portion is covered with a resin; and a manufacturing method thereof. The present invention makes it possible to improve adhesion between the bonding pad portion and ball portion of a bonding wire over an interconnect, thereby improving the reliability of the semiconductor device.Type: GrantFiled: April 8, 2003Date of Patent: March 21, 2006Assignee: Renesas Technology Corp.Inventors: Yasuyuki Nakajima, Toshiaki Morita, Tomoo Matsuzawa, Seiichi Tomoi, Naoki Kawanabe
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Publication number: 20040142551Abstract: Provided is a semiconductor device comprising a first metal film formed above a semiconductor chip, a ball portion formed over said first metal film and made of a second metal, and an alloy layer of said first metal and said second metal which alloy layer is formed between said first metal film and said ball portion, wherein said alloy layer reaches the bottom of said first metal film, and said ball portion is covered with a resin; and a manufacturing method thereof. The present invention makes it possible to improve adhesion between the bonding pad portion and ball portion of a bonding wire over an interconnect, thereby improving the reliability of the semiconductor device.Type: ApplicationFiled: April 8, 2003Publication date: July 22, 2004Applicant: Hitachi, Ltd.Inventors: Yasuyuki Nakajima, Toshiaki Morita, Tomoo Matsuzawa, Seiichi Tomoi, Naoki Watanabe
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Publication number: 20030168740Abstract: Provided is a semiconductor device comprising a first metal film formed above a semiconductor chip, a ball portion formed over said first metal film and made of a second metal, and an alloy layer of said first metal and said second metal which alloy layer is formed between said first metal film and said ball portion, wherein said alloy layer reaches the bottom of said first metal film, and said ball portion is covered with a resin; and a manufacturing method thereof. The present invention makes it possible to improve adhesion between the bonding pad portion and ball portion of a bonding wire over an interconnect, thereby improving the reliability of the semiconductor device.Type: ApplicationFiled: February 21, 2003Publication date: September 11, 2003Inventors: Yasuyuki Nakajima, Toshiaki Morita, Tomoo Matsuzawa, Seiichi Tomoi, Naoki Kawanabe