Patents by Inventor Seiichi URAMOTO
Seiichi URAMOTO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11762497Abstract: A peripheral wiring region of a display device includes a first insulating layer on a substrate, a first wiring layer on the first insulating layer, a second insulating layer which is present on the first insulating layer and covers the first wiring layer, and a second wiring layer on the second insulating layer. A plurality of video signal wirings are arranged in the first wiring layer. A plurality of touch detection wirings arranged in a matrix in an X direction and a Y direction and a conductor pattern to which a fixed potential is supplied are formed in the second wiring layer. The conductor pattern is arranged at a position overlapping a part of the plurality of video signal wirings and is capacitively coupled to the part of the plurality of video signal wirings.Type: GrantFiled: June 28, 2022Date of Patent: September 19, 2023Assignee: JAPAN DISPLAY INC.Inventors: Kazune Matsumura, Seiichi Uramoto, Gen Koide
-
Publication number: 20230004055Abstract: A peripheral wiring region of a display device includes a first insulating layer on a substrate, a first wiring layer on the first insulating layer, a second insulating layer which is present on the first insulating layer and covers the first wiring layer, and a second wiring layer on the second insulating layer. A plurality of video signal wirings are arranged in the first wiring layer. A plurality of touch detection wirings arranged in a matrix in an X direction and a Y direction and a conductor pattern to which a fixed potential is supplied are formed in the second wiring layer. The conductor pattern is arranged at a position overlapping a part of the plurality of video signal wirings and is capacitively coupled to the part of the plurality of video signal wirings.Type: ApplicationFiled: June 28, 2022Publication date: January 5, 2023Applicant: Japan Display Inc.Inventors: Kazune MATSUMURA, Seiichi URAMOTO, Gen KOIDE
-
Patent number: 9829734Abstract: According to one embodiment, a liquid crystal display device includes an array substrate, a counter-substrate and a liquid crystal layer. The array substrate includes a common electrode, an insulating film, a first pixel electrode, a second pixel electrode and a shield electrode. The insulating film is provided on the common electrode. The first pixel electrode and the second pixel electrode are provided on the insulating film and located with an interval therebetween. The shield electrode is provided on the insulating film and located between the first pixel electrode and the second pixel electrode.Type: GrantFiled: December 15, 2014Date of Patent: November 28, 2017Assignee: Japan Display Inc.Inventor: Seiichi Uramoto
-
Patent number: 9627412Abstract: The invention provides a high-precision display device having a reliable top- and single-gate TFT causing less current leakage. Part of a gate line 10 that crosses a semiconductor layer 103 acts as a gate electrode to form a TFT. The semiconductor layer 103 is connected to a data line 20 via a through-hole 140 on one side of the TFT and also connected to a contact electrode 107 via a through-hole 120 on the other side of the TFT. A floating electrode 30 is formed between the TFT and the through-hole 140 or between the TFT and the through-hole 120. The floating electrode 30 is formed on a layer above the semiconductor layer 103 with the use of the same material and at the same time as the gate electrode.Type: GrantFiled: July 1, 2015Date of Patent: April 18, 2017Assignee: Japan Display Inc.Inventor: Seiichi Uramoto
-
Publication number: 20160005769Abstract: The invention provides a high-precision display device having a reliable top- and single-gate TFT causing less current leakage. Part of a gate line 10 that crosses a semiconductor layer 103 acts as a gate electrode to form a TFT. The semiconductor layer 103 is connected to a data line 20 via a through-hole 140 on one side of the TFT and also connected to a contact electrode 107 via a through-hole 120 on the other side of the TFT. A floating electrode 30 is formed between the TFT and the through-hole 140 or between the TFT and the through-hole 120. The floating electrode 30 is formed on a layer above the semiconductor layer 103 with the use of the same material and at the same time as the gate electrode.Type: ApplicationFiled: July 1, 2015Publication date: January 7, 2016Inventor: Seiichi URAMOTO
-
Patent number: 9224756Abstract: According to one embodiment, a display device includes a semiconductor including a first channel region, a second channel region, a source region, a drain region, a first region located between the source region and the first channel region, a second region formed between the first channel region and the second channel region, and a third region located between the drain region and the second channel region, wherein the second region has a length of 5 ?m or more, which is greater than a length of each of the first region and the third region.Type: GrantFiled: February 18, 2014Date of Patent: December 29, 2015Assignee: Japan Display Inc.Inventor: Seiichi Uramoto
-
Publication number: 20150177578Abstract: According to one embodiment, a liquid crystal display device includes an array substrate, a counter-substrate and a liquid crystal layer. The array substrate includes a common electrode, an insulating film, a first pixel electrode, a second pixel electrode and a shield electrode. The insulating film is provided on the common electrode. The first pixel electrode and the second pixel electrode are provided on the insulating film and located with an interval therebetween. The shield electrode is provided on the insulating film and located between the first pixel electrode and the second pixel electrode.Type: ApplicationFiled: December 15, 2014Publication date: June 25, 2015Applicant: Japan Display Inc.Inventor: Seiichi URAMOTO
-
Publication number: 20140239304Abstract: According to one embodiment, a display device includes a semiconductor including a first channel region, a second channel region, a source region, a drain region, a first region located between the source region and the first channel region, a second region formed between the first channel region and the second channel region, and a third region located between the drain region and the second channel region, wherein the second region has a length of 5 ?m or more, which is greater than a length of each of the first region and the third region.Type: ApplicationFiled: February 18, 2014Publication date: August 28, 2014Applicant: Japan Display Inc.Inventor: Seiichi URAMOTO
-
Publication number: 20080036722Abstract: To effectively perform an MF drive by using a simple configuration, a scanning line drive circuit for a display device includes scanning-line driving shift registers serially disposed at a plurality of stages; first switch elements each connected between an output terminal of a first one of the scanning-line driving shift registers and an input terminal of a second scanning-line driving shift register disposed at the following stage; second switch elements each connected between the output terminal of a first one of the scanning-line driving shift registers and the input terminal of a third scanning-line driving shift register disposed at the N+1-th stage following the first scanning-line driving shift register; and a control circuit which controls the first switch elements and the second switch elements.Type: ApplicationFiled: July 23, 2007Publication date: February 14, 2008Applicant: Toshiba Matsushita Display Technology Co., Ltd.Inventors: Seiichi URAMOTO, Tetsuo MORITA