Patents by Inventor Seiichiro INOKUCHI

Seiichiro INOKUCHI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220278004
    Abstract: An insulating substrate (2) is provided on a base plate (1). A semiconductor device (6-9) is provided on the insulating substrate (2). A case (10) is arranged to surround the insulating substrate and the semiconductor device and bonded to the base plate (1) with an adhesive (11). A sealant (22) seals the insulating substrate and the semiconductor device in the case (10). A groove (23) is provided on a lower surface of the case (10) opposing an upper surface peripheral portion of the base plate (1). A bottom surface of the groove (23) has a protruding part (24) protruding toward the base plate (1). The protruding part (24) includes a vertex (25) and gradients (26,27) respectively provided on an inner side and on an outer side of the case (10) with the vertex (25) sandwiched therebetween. The adhesive (11) contacts the vertex (25) and is housed in the groove (23).
    Type: Application
    Filed: November 27, 2019
    Publication date: September 1, 2022
    Applicant: Mitsubishi Electric Corporation
    Inventors: Hiroya SANNAI, Seiichiro INOKUCHI, Yuji IMOTO, Arata IIZUKA
  • Patent number: 11232991
    Abstract: A semiconductor apparatus includes a metal base plate, an upper surface ceramic substrate provided on an upper surface of the metal base plate, a semiconductor device provided on the upper surface ceramic substrate, and a substrate that is provided in the metal base plate and includes an embedded ceramic substrate, an upper surface metal pattern provided on an upper surface of the embedded ceramic substrate, and a lower surface metal pattern provided on a lower surface of the embedded ceramic substrate, wherein a thermal conductivity of the upper surface metal pattern and a thermal conductivity of the lower surface metal pattern are larger than a thermal conductivity of the metal base plate.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: January 25, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shoji Saito, Seiichiro Inokuchi
  • Publication number: 20190371688
    Abstract: A semiconductor apparatus includes a metal base plate, an upper surface ceramic substrate provided on an upper surface of the metal base plate, a semiconductor device provided on the upper surface ceramic substrate, and a substrate that is provided in the metal base plate and includes an embedded ceramic substrate, an upper surface metal pattern provided on an upper surface of the embedded ceramic substrate, and a lower surface metal pattern provided on a lower surface of the embedded ceramic substrate, wherein a thermal conductivity of the upper surface metal pattern and a thermal conductivity of the lower surface metal pattern are larger than a thermal conductivity of the metal base plate.
    Type: Application
    Filed: February 23, 2017
    Publication date: December 5, 2019
    Applicant: Mitsubishi Electric Corporation
    Inventors: Shoji SAITO, Seiichiro INOKUCHI
  • Patent number: 9515061
    Abstract: A semiconductor module includes first and second semiconductor elements connected in series, an insulating substrate, first and second metal patterns formed on a first main surface and a second main surface of the insulating substrate, and first, second, and third electrode plates. A lower surface electrode and an upper surface electrode of the first semiconductor element are bonded to the first metal pattern and the first electrode plate, respectively. The first metal pattern and the third electrode plate are bonded together. An upper surface electrode of the second semiconductor element is bonded to the third electrode plate. A lower surface electrode of the second semiconductor element is electrically connected to the second metal pattern. The second metal pattern and the second electrode plate are bonded together. One end of the first electrode plate and one end of the second electrode plate are led out on the same side.
    Type: Grant
    Filed: October 6, 2015
    Date of Patent: December 6, 2016
    Assignee: Mitsubishi Electric Corporation
    Inventors: Seiichiro Inokuchi, Arata Iizuka
  • Patent number: 9472538
    Abstract: Fixing a semiconductor element to a substrate, electrically connecting signal and main terminals to the semiconductor element, a terminal aggregate includes a frame portion, the signal terminal, the main terminal, which has a larger width than the signal terminal, and a dummy terminal, and forming a to-be-encapsulated body in which the substrate, the semiconductor element, and the terminal aggregate are integrated, mounting the to-be-encapsulated body on a lower mold half such that a plurality of blocks formed in the lower mold half are meshed with the signal, main, and dummy terminals with no space left therebetween after the mounting, placing a bottom surface of an upper mold half on top surfaces of the plurality of blocks, and top surfaces of the signal, main, and dummy terminals to form a cavity for the substrate and the semiconductor element, and performing molding by injecting mold resin into the cavity are included.
    Type: Grant
    Filed: July 4, 2013
    Date of Patent: October 18, 2016
    Assignee: Mitsubishi Electric Corporation
    Inventors: Seiichiro Inokuchi, Mitsunori Aiko, Shintaro Araki, Natsuki Tsuji
  • Publication number: 20160181232
    Abstract: A semiconductor module includes first and second semiconductor elements connected in series, an insulating substrate, first and second metal patterns formed on a first main surface and a second main surface of the insulating substrate, and first, second, and third electrode plates. A lower surface electrode and an upper surface electrode of the first semiconductor element are bonded to the first metal pattern and the first electrode plate, respectively. The first metal pattern and the third electrode plate are bonded together. An upper surface electrode of the second semiconductor element is bonded to the third electrode plate. A lower surface electrode of the second semiconductor element is electrically connected to the second metal pattern. The second metal pattern and the second electrode plate are bonded together. One end of the first electrode plate and one end of the second electrode plate are led out on the same side.
    Type: Application
    Filed: October 6, 2015
    Publication date: June 23, 2016
    Applicant: Mitsubishi Electric Corporation
    Inventors: Seiichiro INOKUCHI, Arata IIZUKA
  • Publication number: 20160079221
    Abstract: Fixing a semiconductor element to a substrate, electrically connecting signal and main terminals to the semiconductor element, a terminal aggregate includes a frame portion, the signal terminal, the main terminal, which has a larger width than the signal terminal, and a dummy terminal, and forming a to-be-encapsulated body in which the substrate, the semiconductor element, and the terminal aggregate are integrated, mounting the to-be-encapsulated body on a lower mold half such that a plurality of blocks formed in the lower mold half are meshed with the signal, main, and dummy terminals with no space left therebetween after the mounting, placing a bottom surface of an upper mold half on top surfaces of the plurality of blocks, and top surfaces of the signal, main, and dummy terminals to form a cavity for the substrate and the semiconductor element, and performing molding by injecting mold resin into the cavity are included.
    Type: Application
    Filed: July 4, 2013
    Publication date: March 17, 2016
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Seiichiro INOKUCHI, Mitsunori AIKO, Shintaro ARAKI, Natsuki TSUJI
  • Patent number: D903611
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: December 1, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hiroya Sannai, Tatsuya Kawase, Seiichiro Inokuchi, Naoki Higashikawa