Patents by Inventor Seiichiro Kawamura

Seiichiro Kawamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5294556
    Abstract: A method of forming a semiconductor-on-insulator device comprises the steps of forming a first alignment mark on a semiconductor substrate at a first reference position, forming a diffusion region in the semiconductor substrate at a position defined with respect to the first alignment mark according to a predetermined relationship, providing an insulator layer on the semiconductor substrate to expose a part of an upper major surface of the semiconductor substrate, providing a semiconductor layer on the insulator layer in contact with the exposed upper major surface of the semiconductor substrate, recrystallizing the semiconductor layer by heating up to a temperature above a melting point of the semiconductor layer and cooling down subsequently below the melting point, starting from a part of the semiconductor layer in contact with the exposed upper major surface of the semiconductor substrate and moving laterally along the semiconductor layer, to form a single crystal semiconductor layer having an upper major
    Type: Grant
    Filed: July 19, 1991
    Date of Patent: March 15, 1994
    Assignee: Fujitsu Limited
    Inventor: Seiichiro Kawamura
  • Patent number: 5116768
    Abstract: A method of fabricating a semiconductor integrated circuit carrying a first type semiconductor device wherein at least a part thereof is formed within a substrate and a second type semiconductor device which is provided on an oxide layer formed on the substrate, comprises steps of providing a silicon nitride film on the substrate selectively in correspondence to where the first type semiconductor device is to be formed, oxidizing the substrate using the silicon nitride film as an oxidation resistant mask to form an oxide layer in correspondence to where the substrate is not covered by the silicon nitride film, depositing a silicon layer on the substrate so as to bury thereunder the silicon nitride film and the oxide layer, annealing the silicon layer such that the silicon layer is caused to melt and crystallized subsequently to form a single crystal silicon layer, and patterning the single crystal silicon layer such that the single crystal silicon layer is removed except for a part thereof covering a region o
    Type: Grant
    Filed: March 20, 1990
    Date of Patent: May 26, 1992
    Assignee: Fujitsu Limited
    Inventor: Seiichiro Kawamura
  • Patent number: 5011783
    Abstract: A method for producing a semiconductor device including the steps of forming an insulating layer on a substrate, the insulating layer having a plurality of concave portions, forming a non-single crystalline silicon layer on the surface of the insulating layer. The non-single crystalline silicon is patterned so that each concave portion is independently melted and the patterned non-single crystalline silicon layer flows into each of the concave portions to form a single crystalline region by irradiation with an energy ray; and, a semiconductor element is also formed in the single crystalline region.
    Type: Grant
    Filed: July 16, 1990
    Date of Patent: April 30, 1991
    Assignee: Fujitsu Limited
    Inventors: Tsutomu Ogawa, Hajime Kamioka, Seiichiro Kawamura, Junji Sakurai
  • Patent number: 4589951
    Abstract: A large single-crystalline film on an amorphous insulator is formed by high energy beam annealing. The crystal growth of a molten polycrystalline or amorphous film on the insulator is controlled to occur from the central region toward the outer edge of the molten zone. This control is accomplished by using, for example, a doughnut-shaped laser beam.
    Type: Grant
    Filed: December 19, 1984
    Date of Patent: May 20, 1986
    Assignee: Fujitsu Limited
    Inventor: Seiichiro Kawamura
  • Patent number: 4584025
    Abstract: A process for fabricating a substrate having a dielectrically isolated region, using energy beam recrystallization. An island of polysilicon is formed on an insulating substrate and a cap containing a dopant is coated on the entire surface of the substrate. A laser beam is irradiated through the cap, and the polysilicon is recrystallized to form a doped first single crystal silicon layer. A second single crystal silicon layer is grown over the first single crystal layer. The first single crystal layer is used as a buried layer, and a semiconductor device is fabricated in the second single crystal layer. This process avoids the existence of crystal imperfections at the boundaries of the single crystal layers.
    Type: Grant
    Filed: November 26, 1984
    Date of Patent: April 22, 1986
    Assignee: Fujitsu Limited
    Inventors: Matsuo Takaoka, Nobuo Sasaki, Seiichiro Kawamura, Osamu Hataishi