Abstract: According to one embodiment, a memory system includes a memory controller and a non-volatile memory electrically connected to the memory controller. The non-volatile memory includes a memory chip having a plurality of planes. The memory chip includes a mode switching circuit and an input and output circuit. The mode switching circuit is configured to switch from a first mode to a second mode in response to a first command from the memory controller. The input and output circuit is configured to receive at least one of a command, an address, or data from the memory controller via a first bus when the mode switching circuit is in the first mode, and transmit, to the memory controller via the first bus, busy information indicating that at least one of the plurality of planes is in a busy state when the mode switching circuit is in the second mode.

Abstract: According to one embodiment, a memory system, comprises a non-volatile memory; a first memory and a second memory; and a memory controller configured to receive a first logical address from a host in a first reading, read a first address conversion table corresponding to the first logical address from the non-volatile memory, and store, in the non-volatile memory, a second address conversion table of a first state stored in the first memory in a case where the first logical address corresponds to a second logical address stored in the second memory.

Abstract: According to one embodiment, a memory system, comprises a non-volatile memory; a first memory and a second memory; and a memory controller configured to receive a first logical address from a host in a first reading, read a first address conversion table corresponding to the first logical address from the non-volatile memory, and store, in the non-volatile memory, a second address conversion table of a first state stored in the first memory in a case where the first logical address corresponds to a second logical address stored in the second memory.