Abstract: A touch panel device includes a cover panel having a front surface including an operation region on which a touch operation is performed and a back surface as a surface on a side opposite to the front surface, a first adhesive material provided on the back surface, a touch panel unit that includes a base substrate and a plurality of touch sensor electrodes provided on a region of the base substrate corresponding to the operation region and is arranged to face the back surface via the first adhesive material, a first displacement detection electrode provided on a part of the back surface outside a region of the back surface corresponding to the operation region, and a second displacement detection electrode provided on a part of the base substrate outside the region of the base substrate corresponding to the operation region to face the first displacement detection electrode.

Abstract: An oscillator circuit includes a first comparator that outputs a first signal indicative of a comparison result between an input potential and a threshold, a second comparator that outputs a second signal indicative of a comparison result between an input potential and the threshold, a RS flip-flop circuit that receives the first signal and the second signal and outputs first and second oscillation signals, a first charge/discharge unit that charges and discharges a first capacitor based on the first oscillation signal, a second charge/discharge unit that charges and discharges a second capacitor based on the second oscillation signal, a first dummy switch controlled to be on and off according to the second oscillation signal and adding a predetermined capacity to a first node, and a second dummy switch controlled to be on and off according to the first oscillation signal and adding a predetermined capacity to a second node.

Abstract: There is provided an output circuit including: an output terminal at which a high-level signal or a low-level signal is outputted; a first resistance element of which one end is connected to the output terminal, the high-level signal passing through the first resistance element; and a second resistance element of which one end is connected to the output terminal, the low-level signal passing through the second resistance element.

Abstract: An oscillator circuit includes a first comparator that outputs a first signal indicative of a comparison result between an input potential and a threshold, a second comparator that outputs a second signal indicative of a comparison result between an input potential and the threshold, a RS flip-flop circuit that receives the first signal and the second signal and outputs first and second oscillation signals, a first charge/discharge unit that charges and discharges a first capacitor based on the first oscillation signal, a second charge/discharge unit that charges and discharges a second capacitor based on the second oscillation signal, a first dummy switch controlled to be on and off according to the second oscillation signal and adding a predetermined capacity to a first node, and a second dummy switch controlled to be on and off according to the first oscillation signal and adding a predetermined capacity to a second node.

Abstract: A power-on clear circuit includes a bias current generation circuit having one end connected to a first line supplied with a first power supply voltage, the other end connected to a second line kept at a fixed potential, and configured to generate a bias current, and to transmit the bias current to a first node; a first transistor having a first terminal connected to the second line, a second terminal connected to the first node, and a control terminal for receiving application of a second power supply voltage which varies to follow the first power supply voltage; an inverter unit configured to operate on the basis of the first power supply voltage, and to which a potential of the first node is input; and a signal outputting unit configured to output a power-on clear signal in accordance with an output of the inverter unit.

Abstract: A power-on clear circuit includes a first inverter unit including a constant current transmission unit having one end supplied with a first power supply voltage, and a first transistor having a first terminal connected to a second line kept at a fixed potential, a second terminal connected to the other end of the constant current transmission unit, and a control terminal receiving application of a second power supply voltage which varies to follow the first power supply voltage; a second inverter unit that operates on the basis of the first power supply voltage, and to which a potential of a first node is input, the first node is connected between the other end of the constant current transmission unit and the first terminal of the first transistor; and a signal outputting unit that outputs a power-on clear signal in accordance with an output of the second inverter unit.

Abstract: A power-on clear circuit comprises: a first inverter unit including a constant current transmission unit having one end supplied with a first power supply voltage, and a first transistor having a first terminal connected to a second line kept at a fixed potential, a second terminal connected to the other end of the constant current transmission unit, and a control terminal for receiving application of a second power supply voltage which varies to follow the first power supply voltage; a second inverter unit configured to operate on the basis of the first power supply voltage, and to which a potential of a first node is input, the first node is connected between the other end of the constant current transmission unit and the first terminal of the first transistor; and a signal outputting unit configured to output a power-on clear signal in accordance with an output of the second inverter unit.

Abstract: A power-on clear circuit which comprises: a bias current generation circuit having one end connected to a first line supplied with a first power supply voltage, the other end connected to a second line kept at a fixed potential, and is configured to generate a bias current, and to transmit the bias current to a first node; a first transistor having a first terminal connected to the second line, a second terminal connected to the first node, and a control terminal for receiving application of a second power supply voltage which varies to follow the first power supply voltage; an inverter unit configured to operate on the basis of the first power supply voltage, and to which a potential of the first node is input; and a signal outputting unit configured to output a power-on clear signal in accordance with to an output of the inverter unit.

Abstract: A resistor array made of a semiconductor includes a plurality of resistor groups and a common line that electrically connects the M-th resistors of the plurality of resistor groups. Each resistor group includes first to M-th resistors connected in series, M being an integer of 2 or greater, and at least one short-circuit line, each short-circuiting at least one, but not all, of the M resistors.

Abstract: A resistor array made of a semiconductor includes a plurality of resistor groups and a common line that electrically connects the M-th resistors of the plurality of resistor groups. Each resistor group includes first to M-th resistors connected in series, M being an integer of 2 or greater, and at least one short-circuit line, each short-circuiting at least one, but not all, of the M resistors.

Abstract: In a pipelined analog-to-digital (AD) converter, if logically incongruent signals S1 and S2 are output from an AD converter section of a converter stage of the AD converter, a digital-to-analog converter (DAC) section is to be prevented from erroneously operating. When a logically incongruent combination of signals S1 and S2, such as S1=“H” and S2=“L”, is output from comparators that compare an input voltage VI to reference voltages +REF/4 and ?REF/4, an encoder outputs a signal corresponding to a normal signal combination (S1=“L” and S2=“H”) to generate signals X, Y and Z that control switches of the DAC section. This eliminates the risk that the switches shall be turned on simultaneously, thus preventing the erroneous operation of the DAC section.

Abstract: In a pipelined analog-to-digital (AD) converter, if logically incongruent signals S1 and S2 are output from an AD converter section of a converter stage of the AD converter, a digital-to-analog converter (DAC) section is to be prevented from erroneously operating. When a logically incongruent combination of signals S1 and S2, such as S1=“H” and S2=“L”, is output from comparators that compare an input voltage VI to reference voltages +REF/4 and ?REF/4, an encoder outputs a signal corresponding to a normal signal combination (S1=“L” and S2=“H”) to generate signals X, Y and Z that control switches of the DAC section. This eliminates the risk that the switches shall be turned on simultaneously, thus preventing the erroneous operation of the DAC section.

Abstract: A resistance dividing circuit including silicide layers respectively formed only on branch portions of a linear polysilicon resistance wiring having the branch portions. Contact plugs are connected to the resistance wiring via the silicide layers, and fetching electrodes are respectively connected to the contact plugs.

Abstract: A current-cell type D/A converter using a timing generating circuit for converting a digital code to the corresponding differential voltage Vout between a first analog voltage and a second voltage includes a plural of current cells and a plural of switch-control-signal generating circuits generating each of switch-control signals being provided each of the above current cells. Each of the above current cells includes the switching NMOSs, and the constant-current sources of the NMOSs.

Abstract: The present invention provides a multilayered power supply line suitable for use in a semiconductor integrated circuit and a layout method thereof. In the multilayered power supply line (10) for the semiconductor integrated circuit, a top metal (12) and a second metal (14) are electrically connected to each other by through holes (18). Further, a capacitor metal (16) is electrically connected to the top metal (12) by through holes (20) to thereby make the top metal (12), the second metal (14) and the capacitor metal (16) identical in potential to one another, whereby the multilayered power supply line functions as a power supply line based on normal wiring metals without functioning as a capacitor. It is thus possible to supply power with reduced impedance.

Abstract: A current-cell type D/A converter using a timing generating circuit for converting a digital code to the corresponding differential voltage Vout between a first analog voltage and a second voltage includes a plural of current cells and a plural of switch-control-signal generating circuits generating each of switch-control signals being provided each of the above current cells. Each of the above current cells includes the switching NMOSs, and the constant-current sources of the NMOSs.

Abstract: According to the present invention, a multi-layered capacitor includes a first capacitive element having a first conductor plate formed on a first layer, a second conductor plate formed on a second layer and an insulator arranged between the first and second conductor plates; and a second capacitive element which is arranged just on a layer above or below the first capacitive element.

Abstract: A resistance dividing circuit including silicide layers respectively formed only on branch portions of a linear polysilicon resistance wiring having the branch portions. Contact plugs are connected to the resistance wiring via the silicide layers, and fetching electrodes are respectively connected to the contact plugs.

Abstract: A resistance dividing circuit including silicide layers respectively formed only on branch portions of a linear polysilicon resistance wiring having the branch portions. Contact plugs are connected to the resistance wiring via the silicide layers, and fetching electrodes are respectively connected to the contact plugs.

Abstract: The present invention provides a resistance dividing circuit wherein silicide layers are respectively formed only on branch portions of a linear polysilicon resistance wiring having the branch portions, contact plugs connected to the resistance wiring via the silicide layers have connections, and fetching electrodes respectively connected to the contact plugs are provided.