Patents by Inventor Seiichiro Shirai

Seiichiro Shirai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8557611
    Abstract: An exposure apparatus includes a light emission part 10 generating EUV light by plasma excitation of a predetermined atom, a condenser part 20 condensing the EUV light emitted from the light emission part, an exposure part 30 irradiating a substrate via a mask with the EUV light condensed by the condenser part, a first plasma position monitor 11a detecting the position of an emission point of the EUV light within the light emission part, and a light emission part drive unit 13 adjusting the position of the light emission part. The exposure apparatus determines a first shift amount between the emission point detected by the plasma position monitor and a reference light emission position, and drives the light emission part drive unit according to the first shift amount.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: October 15, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Seiichiro Shirai
  • Publication number: 20120156623
    Abstract: A semiconductor device manufacturing method which improves exposure characteristics. The method includes the step of making preparations for use of an exposure apparatus. The apparatus includes a light emitting unit with a first electrode and a second electrode for generating EUV light, a heating light source for heating the first electrode and the second electrode, and an exposure unit for projecting the EUV light on a substrate through a mask. The method also includes the following steps: heating the first electrode and the second electrode by the heating light source; after the heating step, applying a voltage between the first electrode and the second electrode and generating EUV light by plasma excitation of predetermined atoms; and leading the EUV light into the exposure unit and making an exposure on a photosensitive film formed over the substrate inside the exposure unit.
    Type: Application
    Filed: December 7, 2011
    Publication date: June 21, 2012
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Seiichiro SHIRAI
  • Publication number: 20120156809
    Abstract: An exposure apparatus includes a light emission part 10 generating EUV light by plasma excitation of a predetermined atom, a condenser part 20 condensing the EUV light emitted from the light emission part, an exposure part 30 irradiating a substrate via a mask with the EUV light condensed by the condenser part, a first plasma position monitor 11a detecting the position of an emission point of the EUV light within the light emission part, and a light emission part drive unit 13 adjusting the position of the light emission part. The exposure apparatus determines a first shift amount between the emission point detected by the plasma position monitor and a reference light emission position, and drives the light emission part drive unit according to the first shift amount.
    Type: Application
    Filed: November 29, 2011
    Publication date: June 21, 2012
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Seiichiro SHIRAI
  • Publication number: 20110074049
    Abstract: A method of manufacturing a semiconductor device answerable to refinement of circuits by correctly connecting adjacent small patterns with each other with excellent reproducibility in connective exposure and a semiconductor device manufactured by this method are proposed. According to this method of manufacturing a semiconductor device, connective exposure is performed by dividing a pattern formed on a semiconductor substrate into a plurality of patterns and exposing the plurality of divided patterns in a connective manner, by forming marks for adjusting arrangement of the patterns to be connected with each other on the semiconductor substrate before exposing patterns of a semiconductor element and connectively exposing the patterns of the semiconductor element in coincidence with the marks for adjusting arrangement.
    Type: Application
    Filed: December 10, 2010
    Publication date: March 31, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinroku Maejima, Seiichiro Shirai, Takahiro Machida
  • Patent number: 7875409
    Abstract: A method of manufacturing a semiconductor device answerable to refinement of circuits by correctly connecting adjacent small patterns with each other with excellent reproducibility in connective exposure and a semiconductor device manufactured by this method are proposed. According to this method of manufacturing a semiconductor device, connective exposure is performed by dividing a pattern formed on a semiconductor substrate into a plurality of patterns and exposing the plurality of divided patterns in a connective manner, by forming marks for adjusting arrangement of the patterns to be connected with each other on the semiconductor substrate before exposing patterns of a semiconductor element and connectively exposing the patterns of the semiconductor element in coincidence with the marks for adjusting arrangement.
    Type: Grant
    Filed: November 21, 2006
    Date of Patent: January 25, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Shinroku Maejima, Seiichiro Shirai, Takahiro Machida
  • Publication number: 20070134564
    Abstract: A method of manufacturing a semiconductor device answerable to refinement of circuits by correctly connecting adjacent small patterns with each other with excellent reproducibility in connective exposure and a semiconductor device manufactured by this method are proposed. According to this method of manufacturing a semiconductor device, connective exposure is performed by dividing a pattern formed on a semiconductor substrate into a plurality of patterns and exposing the plurality of divided patterns in a connective manner, by forming marks for adjusting arrangement of the patterns to be connected with each other on the semiconductor substrate before exposing patterns of a semiconductor element and connectively exposing the patterns of the semiconductor element in coincidence with the marks for adjusting arrangement.
    Type: Application
    Filed: November 21, 2006
    Publication date: June 14, 2007
    Inventors: Shinroku Maejima, Seiichiro Shirai, Takahiro Machida
  • Publication number: 20070076203
    Abstract: An exposure apparatus includes an illumination optical system having an exposure light source for emitting an exposure light, a projection optical system for guiding the exposure light to a substrate, a detection light source for emitting the detection light for detecting a focal point at a time of exposure, a polarizer capable of polarizing the detection light emitted from the detection light source into a specified polarized light, and a light detector for detecting the detection light polarized into the specified polarized light by the polarizer.
    Type: Application
    Filed: September 26, 2006
    Publication date: April 5, 2007
    Applicant: Renesas Technology Corp.
    Inventors: Takeo Ishibashi, Seiichiro Shirai
  • Patent number: 6436220
    Abstract: The present invention is intended to collectively remove unnecessary resist material and side wall protective film after dry etching by side wall protection process, making it possible to simplify the process for the preparation of semiconductors, etc. The process according to the present invention comprises removing unnecessary resist material (3) left behind after dry etching by side wall protection process with a resist pattern (3) present on a semiconductor substrate (2) as a mask and side wall protective film (4) deposited on the side wall (22) of pattern, said process comprising the steps of applying an pressure-sensitive adhesive sheet (1) to said substrate (2), heating the pressure-sensitive adhesive layer (1) under pressure so that the pressure-sensitive adhesive (11) comes in contact with up to the side wall (4) of pattern, and then collectively peeling said pressure-sensitive adhesive sheet (1), said resist material (3) and said side wall protective film (4) off said substrate.
    Type: Grant
    Filed: August 10, 1999
    Date of Patent: August 20, 2002
    Assignee: Nitto Denko Corporation
    Inventors: Eiji Toyoda, Makoto Namikawa, Kouichi Hashimoto, Seiichiro Shirai
  • Patent number: 6329112
    Abstract: Optical systems of projection exposure apparatuses may have aberrations, and this fact may hamper the achievement of predetermined accuracy of dimensions and position of a circuit pattern which is necessary to attain desired device performance. Further, because of the difficulty in measuring the above-described aberrations, it was not possible to correct the optical system so as to realize a substantially aberration-free characteristic. The aberrations of a projection lens can be found accurately by steps of: measuring the light intensities of a projected image of a particular pattern on a mask at n different points in the projected image; and solving n simultaneous equations with m (m<n) unknown weighting coefficients for m known wavefront aberration functions. Based on the aberrations thus found, one can adjust aberration characteristic of the projection lens or correct dimensions and positions of patterns on a mask instead.
    Type: Grant
    Filed: November 12, 1999
    Date of Patent: December 11, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Fukuda, Seiichiro Shirai, Tsuneo Terasawa, Katsuya Hayano, Norio Hasegawa
  • Patent number: 5959011
    Abstract: A method for removing a resist pattern formed on a semiconductor wafer, and a curable pressure-sensitive adhesive, adhesive sheets and an apparatus used for the method. The resist-removing method comprising adhering an adhesive tape on an upper surface of a resist pattern formed on an article and peeling off the resist pattern together with the adhesive tape; the curable pressure-sensitive adhesive constituting the adhesive tape, comprising a pressure-sensitive adhesive polymer containing a non-volatile compound having at least one unsaturated double bond in the molecule and having a good affinity with a resist material to be removed; the adhesive sheet comprising a film substrate having formed thereon the curable pressure-sensitive adhesive; and the resist-removing apparatus comprising a means for press-adhering the adhesive tape, a tape-peeling means, and a substrate-washing means.
    Type: Grant
    Filed: November 18, 1996
    Date of Patent: September 28, 1999
    Assignees: Nitto Denko Corporation, Hitachi, Ltd.
    Inventors: Fumio Mizuno, Noburu Moriuchi, Seiichiro Shirai, Yutaka Moroishi, Makoto Sunakawa, Michirou Kawanishi
  • Patent number: 5736300
    Abstract: One object of the present invention is to provide the reduced projection exposure method which enables the exposure of various and fine patterns in manufacturing process of semiconductor devices or semiconductor integrated circuit devices. Structure of the present invention to attain the above object is to carry out the reduced projection exposure using a phase shift mask provided with a prescribed correction pattern on the end of the mask pattern domain of a constant mode or the boundary of the mask pattern domain of plural modes. According to this structure, as the end effects etc. are canceled by the correction pattern, the various and fine patterns can be exposed.
    Type: Grant
    Filed: August 8, 1996
    Date of Patent: April 7, 1998
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Fumio Mizuno, Noboru Moriuchi, Seiichiro Shirai, Masayuki Morita
  • Patent number: 5578422
    Abstract: One object of the present invention is to provide the reduced projection exposure method which enables the exposure of various and fine patterns in manufacturing process of semiconductor devices or semiconductor integrated circuit devices. Structure of the present invention to attain the above object is to carry out the reduced projection exposure using a phase shift mask provided with a prescribed correction pattern on the end of the mask pattern domain of a constant mode or the boundary of the mask pattern domain of plural modes. According to this structure, as the end effects etc. are canceled by the correction pattern, the various and fine patterns can be exposed.
    Type: Grant
    Filed: May 18, 1995
    Date of Patent: November 26, 1996
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Fumio Mizuno, Noboru Moriuchi, Seiichiro Shirai, Masayuki Morita
  • Patent number: 5466325
    Abstract: A method for removing a resist pattern formed on a semiconductor wafer, and a curable pressure-sensitive adhesive, adhesive sheets and an apparatus used for the method. The resist-removing method comprising adhering an adhesive tape on an upper surface of a resist pattern formed on an article and peeling off the resist pattern together with the adhesive tape; the curable pressure-sensitive adhesive constituting the adhesive tape, comprising a pressure-sensitive adhesive polymer containing a non-volatile compound having at least one unsaturated double bond in the molecule and having a good affinity with a resist material to be removed; the adhesive sheet comprising a film substrate having formed thereon the curable pressure-sensitive adhesive; and the resist-removing apparatus comprising a means for press-adhering the adhesive tape, a tape-peeling means, and a substrate-washing means.
    Type: Grant
    Filed: August 11, 1994
    Date of Patent: November 14, 1995
    Assignees: Nitto Denko Corporation, Hitachi Ltd.
    Inventors: Fumio Mizuno, Noboru Moriuchi, Seiichiro Shirai, Yutaka Moroishi, Makoto Sunakawa, Michirou Kawanishi
  • Patent number: 5436095
    Abstract: One object of the present invention is to provide the reduced projection exposure method which enables the exposure of various and fine patterns in manufacturing process of semiconductor devices or semiconductor integrated circuit devices. Structure of the present invention to attain the above object is to carry out the reduced projection exposure using a phase shift mask provided with a prescribed correction pattern on the end of the mask pattern domain of a constant mode or the boundary of the mask pattern domain of plural modes. According to this structure, as the end effects etc. are canceled by the correction pattern, the various and fine patterns can be exposed.
    Type: Grant
    Filed: July 13, 1992
    Date of Patent: July 25, 1995
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Fumio Mizuno, Noboru Moriuchi, Seiichiro Shirai, Masayuki Morita
  • Patent number: 5405810
    Abstract: The present invention enables the accuracy of aligning a wafer and a reticle with each other in the exposure step in the manufacture of a semiconductor integrated circuit device to be improved. The portions of a metal film 5 and a resist film 6 which cover an alignment mark 4 on a wafer 1 are removed by a gas assisted etching treatment using a laser beam prior to the execution of an exposure treatment, so as to bare the alignment mark 4. The position detecting light is then applied from an alignment mark position detecting means in a reduction projection exposure unit 11 to the alignment mark 4, the position of the alignment mark 4 being detected on the basis of the light reflected on and scattered from the alignment mark 4.
    Type: Grant
    Filed: April 16, 1992
    Date of Patent: April 11, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Fumio Mizuno, Noboru Moriuchi, Seiichiro Shirai
  • Patent number: 4835089
    Abstract: A thick polymer film containing an aromatic bisazide and/or an aromatic sulfonyl azide compound is formed on a substrate having topography level on its surface to flatten said surface and then heated or the whole surface thereof is exposed to a light. A mask pattern having a dry etching resistance higher than that of the polymer is formed on the polymer film, exposed parts of the polymer film are removed by the dry etching and the exposed parts of the film to be processed are removed to form a pattern.
    Type: Grant
    Filed: June 10, 1987
    Date of Patent: May 30, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Takao Iwayanagi, Norio Hasegawa, Toshihiko Tanaka, Hiroshi Shiraishi, Takumi Ueno, Michiaki Hashimoto, Seiichiro Shirai, Kazuya Kadota
  • Patent number: RE37996
    Abstract: One object of the present invention is to provide the reduced projection exposure method which enables the exposure of various and fine patterns in manufacturing process of semiconductor devices or semiconductor integrated circuit devices. Structure of the present invention to attain the above object is to carry out the reduced projection exposure using a phase shift mask provided with a prescribed correction pattern on the end of the mask pattern domain of a constant mode or the boundary of the mask pattern domain of plural modes. According to this structure, as the end effects etc. are canceled by the correction pattern, the various and fine patterns can be exposed.
    Type: Grant
    Filed: April 6, 2000
    Date of Patent: February 18, 2003
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Fumio Mizuno, Noboru Moriuchi, Seiichiro Shirai, Masayuki Morita