Abstract: A digital phase difference detector detects a phase difference between first and second signals. A delay circuit cumulatively delays the first signal. A flip flop group latches the signals. An edge detector detects a first phase difference between a rise of the first signal and either one of a rise or a fall of the second signal, and a second phase difference between a fall of the first signal and either one of the rise or the fall of the second signal. A memory circuit stores the phase differences. A normalization circuit computes a cycle of the first signal from a difference between previous first and second phase differences stored in the memory circuit and a difference between the first and second phase differences which are currently detected by the edge detector to normalize the phase difference between the first and second signals with reference to the cycle.

Abstract: A variable delay circuit (101) generates a plurality of delay signals (D(1), D(2), . . . , D(n)). An output holding circuit (102) receives the plurality of delay signals (D(1), D(2), . . . , D(n)) in synchronization with a transition of a reference signal (Sref). A selector (104) provides an input signal (Sin) to the variable delay circuit (101) in a normal mode, and provides one of the plurality of delay signals (D(1), D(2), . . . , D(n)) to the variable delay circuit (101) in a calibration mode. A frequency measurement circuit (105) counts the number of transitions of one of the plurality of delay signals (D(1), D(2), . . . , D(n)) during a predetermined frequency measurement period. In the calibration mode, a delay-amount calibration circuit (106) adjusts a delay time of the variable delay circuit (101) so that the number of transitions counted by the frequency measurement circuit (105) approaches a target value corresponding to a frequency of the input signal (Sin).

Abstract: In a PLL circuit including a VCO having a plurality of oscillation frequency bands, a TDC circuit calculates a phase difference between a predetermined reference signal from a fixed frequency divider and a PLL frequency-divided signal from a variable frequency divider. The TDC circuit detects the amount of time by which the phase of the PLL frequency-divided signal leads or lags with respect to that of the reference signal in one cycle of the reference signal, thereby detecting which of the signals has a higher frequency and which has a lower frequency. Therefore, for each oscillation frequency band, the frequency comparison is completed in one cycle of the reference signal, allowing an oscillation frequency band selection circuit to detect an optimum oscillation frequency band corresponding to a predetermined PLL output frequency in a short time.

Abstract: In a PLL circuit including a VCO having a plurality of oscillation frequency bands, a TDC circuit calculates a phase difference between a predetermined reference signal from a fixed frequency divider and a PLL frequency-divided signal from a variable frequency divider on a rising edge of the reference signal and then calculates a phase difference between the reference signal and the PLL frequency-divided signal on the next rising edge of the reference signal in the same manner. From information on the two calculated phase differences, the TDC circuit detects the amount of time by which the phase of the PLL frequency-divided signal leads or lags with respect to that of the reference signal in one cycle of the reference signal, thereby detecting which of the signals, the reference signal or the PLL frequency-divided signal, has a higher frequency and which has a lower frequency.

Abstract: In transmission frequency modulation in radio communication, correspondences to multiple-value frequency modulation having plural-bits transmission data are realized while suppressing an increase in the circuit area. When performing transmission frequency modulation in radio communication, response data of a digital filter are calculated by a logic circuit that is embedded in a transmission modulator. Since a change amount in the division number is calculated by the logic circuit, a ROM for storing the response data is dispensed with, and thereby an increase in the circuit area can be suppressed when the transmission modulator corresponds to variations in the frequency of a reference signal or to multiple-value frequency modulation having plural-bits transmission data. Further, bandwidth narrowing of a transmission signal spectrum is realized by performing the transmission frequency modulation with dividing the process thereof into plural steps using a timing synchronized with a clock.

Abstract: A 6.alpha.-methylprednisolone derivative of the general formula: ##STR1## wherein R.sup.1 is a hydrogen atom or stands for the grouping ##STR2## where R.sup.3 is a straight or once-branched chain C.sub.1-4 alkyl group, a phenyl group or a lower alkoxy- or alkylthio-methyl group, and R.sup.2 is a straight or once-branched chain C.sub.1-4 alkyl group, a phenyl group or a lower alkoxy- or alkylthio-methyl group, with the proviso that when R.sup.2 is ethyl group, R.sup.1 should not be a hydrogen atom or R.sup.3 should not be ethyl group. This compound exhibits a strong local antiinflammatory effect and is, therefore, useful as a harmless external antiinflammatory drug for various dermal disorders and also as an antiallergic drug for treating asthma and the like allergic diseases.