Abstract: A voltage step-up circuit for a non-volatile semiconductor memory which includes a first series of an odd number of inverters (20), a second series of an even number of inverters (21), and a transmission gate (203) provided in the pre-stage inverter of each inverter series to control the potentials inputted to the p-channel and n-channel transistors of the final-stage inverter so that both the transistors are not simultaneously turned on.

Abstract: A high voltage switch circuit, wherein the source of a first MOS transistor is connected to the gate of a second MOS transistor, the source of the second MOS transistor is connected to the gate of the first MOS transistor, the drain of a third MOS transistor and the gate of a fourth MOS transistor, the drains of the first and fourth MOS transistors are connected to a high voltage input terminal, the sources of the third and fourth MOS transistors are connected to an output terminal, a voltage for turning the transistor ON is applied to the gate of the third MOS transistor, one electrodes of two independent capacitors are connected to the gates of the first and second MOS transistors, and a clock is applied through transmission gates to the other electrode of the two capacitors.