Patents by Inventor Seiji Andoh
Seiji Andoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7514768Abstract: A package structure for a semiconductor device comprises a substrate having a main surface and a back surface, a semiconductor chip formed on the main surface of the substrate, a package covering the semiconductor chip, radiation protrude electrodes and connection protrude electrodes. The radiation protrude electrodes are formed on the back surface of the substrate in a chip area where said semiconductor chip is located. Each of the radiation protrude electrodes are formed with a first pitch so that the radiation protrude electrodes make one body joining layer when the package structure is subjected to a heat treatment. The connection protrude electrodes are formed on the back surface of the substrate in a peripheral area of the chip area. Each of the connection protrude electrodes formed with a second pitch which is larger than the first pitch so that the connection protrude electrodes stay individual when the package structure is subjected to a heat treatment.Type: GrantFiled: September 15, 2006Date of Patent: April 7, 2009Assignee: Oki Electric Industry Co., Ltd.Inventor: Seiji Andoh
-
Patent number: 7414304Abstract: A semiconductor device including a substrate having a main surface including a first area, a second area surrounding the first area, and a third area surrounding the second area; a first insulating protective film that is provided in the first area and formed in a shape having no angles; a second insulating protective film provided in the third area; a semiconductor chip that is provided on the first insulating protective film and has a bottom surface facing to the first insulating protective film; and a sealing resin covering the semiconductor chip, wherein the bottom surface of the semiconductor chip covers the first area.Type: GrantFiled: January 5, 2007Date of Patent: August 19, 2008Assignee: Oki Electric Industry Co., Ltd.Inventor: Seiji Andoh
-
Publication number: 20070108636Abstract: A semiconductor device including a substrate having a main surface including a first area, a second area surrounding the first area, and a third area surrounding the second area; a first insulating protective film that is provided in the first area and formed in a shape having no angles; a second insulating protective film provided in the third area; a semiconductor chip that is provided on the first insulating protective film and has a bottom surface facing to the first insulating protective film; and a sealing resin covering the semiconductor chip, wherein the bottom surface of the semiconductor chip covers the first area.Type: ApplicationFiled: January 5, 2007Publication date: May 17, 2007Inventor: Seiji Andoh
-
Patent number: 7208844Abstract: A semiconductor device including a substrate having a main surface including a first area, a second area surrounding the first area, and a third area surrounding the second area; a first insulating protective film that is provided in the first area and formed in a shape having no angles; a second insulating protective film provided in the third area; a semiconductor chip that is provided on the first insulating protective film and has a bottom surface facing to the first insulating protective film; and a sealing resin covering the semiconductor chip, wherein the bottom surface of the semiconductor chip covers the first area.Type: GrantFiled: January 30, 2004Date of Patent: April 24, 2007Assignee: Oki Electric Industry Co., Ltd.Inventor: Seiji Andoh
-
Publication number: 20070008704Abstract: A package structure for a semiconductor device comprises a substrate having a main surface and a back surface, a semiconductor chip formed on the main surface of the substrate, a package covering the semiconductor chip, radiation protrude electrodes and connection protrude electrodes. The radiation protrude electrodes are formed on the back surface of the substrate in a chip area where said semiconductor chip is located. Each of the radiation protrude electrodes are formed with a first pitch so that the radiation protrude electrodes make one body joining layer when the package structure is subjected to a heat treatment. The connection protrude electrodes are formed on the back surface of the substrate in a peripheral area of the chip area. Each of the connection protrude electrodes formed with a second pitch which is larger than the first pitch so that the connection protrude electrodes stay individual when the package structure is subjected to a heat treatment.Type: ApplicationFiled: September 15, 2006Publication date: January 11, 2007Inventor: Seiji Andoh
-
Patent number: 7123480Abstract: A package structure for a semiconductor device comprises a substrate having a main surface and a back surface, a semiconductor chip formed on the main surface of the substrate, a package covering the semiconductor chip, radiation protrude electrodes and connection protrude electrodes. The radiation protrude electrodes are formed on the back surface of the substrate in a chip area where said semiconductor chip is located. Each of the radiation protrude electrodes are formed with a first pitch so that the radiation protrude electrodes make one body joining layer when the package structure is subjected to a heat treatment. The connection protrude electrodes are formed on the back surface of the substrate in a peripheral area of the chip area. Each of the connection protrude electrodes formed with a second pitch which is larger than the first pitch so that the connection protrude electrodes stay individual when the package structure is subjected to a heat treatment.Type: GrantFiled: August 17, 1999Date of Patent: October 17, 2006Assignee: Oki Electric Industry Co., Ltd.Inventor: Seiji Andoh
-
Patent number: 6929979Abstract: A resin sealed type semiconductor device; is provided with a semiconductor chip which has a pad formed on a main surface thereof, an insulating film which is formed on a part of the pad and on the main surface of the semiconductor chip, an interconnection which is formed on a part of the insulating film and which is electrically connected to the pad, a sealing resin which seals the interconnection and the insulating film, a post formed on the interconnection which has a surface exposed to outside of the sealing resin and which is electrically connected to the interconnection, a bump electrode which is mounted on the exposed surface of the post and a radiation post which is formed on the insulating film and which has a surface exposed to outside of the sealing resin.Type: GrantFiled: May 27, 2003Date of Patent: August 16, 2005Assignee: Oki Electric Industry Co., Ltd.Inventor: Seiji Andoh
-
Publication number: 20050093179Abstract: A semiconductor device including a substrate having a main surface including a first area, a second area surrounding the first area, and a third area surrounding the second area; a first insulating protective film that is provided in the first area and formed in a shape having no angles; a second insulating protective film provided in the third area; a semiconductor chip that is provided on the first insulating protective film and has a bottom surface facing to the first insulating protective film; and a sealing resin covering the semiconductor chip, wherein the bottom surface of the semiconductor chip covers the first area.Type: ApplicationFiled: January 30, 2004Publication date: May 5, 2005Applicant: Oki Electric Industry Co., Ltd.Inventor: Seiji Andoh
-
Patent number: 6773966Abstract: A semiconductor device manufacturing method according to the present invention comprising: arranging a dam made of a highly heat-shrinkable material on a surface of a circuit substrate, wherein the dam defines a region including a semiconductor element, a conductor, and part of a conductive pattern connected to one end of the conductor; injecting a sealer into a region defined by the dam and using the sealer to seal the semiconductor element, the conductor, and part of the conductive pattern connecting with one end of the conductor; and cooling the dam to remove it. Namely, the method can decrease costs, shorten the manufacturing time, and provide miniaturized COB-mounted semiconductor devices.Type: GrantFiled: September 30, 2002Date of Patent: August 10, 2004Assignee: Oki Electric Industry Co., Ltd.Inventor: Seiji Andoh
-
Publication number: 20040009630Abstract: A resin sealed type semiconductor device, is provided with a semiconductor chip which has a pad formed on a main surface thereof, an insulating film which is formed on a part of the pad and on the main surface of the semiconductor chip, an interconnection which is formed on a part of the insulating film and which is electrically connected to the pad, a sealing resin which seals the interconnection and the insulating film, a post formed on the interconnection which has a surface exposed to outside of the sealing resin which is electrically connected to the interconnection, a bump electrode which is mounted on the exposed surface of the post and a radiation post which is formed on the insulating film and which has a surface exposed to outside of the sealing resin.Type: ApplicationFiled: May 27, 2003Publication date: January 15, 2004Applicant: Oki Electric Industry Co., Ltd.Inventor: Seiji Andoh
-
Patent number: 6674163Abstract: A package structure for a semiconductor device comprises a substrate having a main surface and a back surface, a semiconductor chip formed on the main surface of the substrate, a package covering the semiconductor chip, radiation protrude electrodes and connection protrude electrodes. The radiation protrude electrodes are formed on the back surface of the substrate in a chip area where said semiconductor chip is located. Each of the radiation protrude electrodes are formed with a first pitch so that the radiation protrude electrodes make one body joining layer when the package structure is subjected to a heat treatment. The connection protrude electrodes are formed on the back surface of the substrate in a peripheral area of the chip area. Each of the connection protrude electrodes formed with a second pitch which is larger than the first pitch so that the connection protrude electrodes stay individual when the package structure is subjected to a heat treatment.Type: GrantFiled: July 20, 2000Date of Patent: January 6, 2004Assignee: Oki Electric Industry Co., Ltd.Inventor: Seiji Andoh
-
Patent number: 6627988Abstract: A resin sealed type semiconductor device is provided with a semiconductor chip which has a pad formed on a main surface thereof, an insulating film which is formed on a part of the pad and on the main surface of the semiconductor chip, an interconnection which is formed on a part of the insulating film and which is electrically connected to the pad, a sealing resin which seals the interconnection and the insulating film, a post formed on the interconnection which has a surface exposed to outside of the sealing resin and which is electrically connected to the interconnection, a bump electrode which is mounted on the exposed surface of the post and a radiation post which is formed on the insulating film and which has a surface exposed to outside of the sealing resin.Type: GrantFiled: February 15, 2001Date of Patent: September 30, 2003Assignee: Oki Electric Industry Co, Ltd.Inventor: Seiji Andoh
-
Publication number: 20030178709Abstract: A semiconductor device manufacturing method according to the present invention comprising: arranging a dam made of a highly heat-shrinkable material on a surface of a circuit substrate, wherein the dam defines a region including a semiconductor element, a conductor, and part of a conductive pattern connected to one end of the conductor; injecting a sealer into a region defined by the dam and using the sealer to seal the semiconductor element, the conductor, and part of the conductive pattern connecting with one end of the conductor; and cooling the dam to remove it. Namely, the method can decrease costs, shorten the manufacturing time, and provide miniaturized COB-mounted semiconductor devices.Type: ApplicationFiled: September 30, 2002Publication date: September 25, 2003Inventor: Seiji Andoh
-
Publication number: 20010028110Abstract: A resin sealed type semiconductor device, is provided with a semiconductor chip which has a pad formed on a main surface thereof, an insulating film which is formed on a part of the pad and on the main surface of the semiconductor chip, an interconnection which is formed on a part of the insulating film and which is electrically connected to the pad, a sealing resin which seals the interconnection and the insulating film, a post formed on the interconnection which has a surface exposed to outside of the sealing resin which is electrically connected to the interconnection, a bump electrode which is mounted on the exposed surface of the post and a radiation post which is formed on the insulating film and which has a surface exposed to outside of the sealing resin.Type: ApplicationFiled: February 15, 2001Publication date: October 11, 2001Inventor: Seiji Andoh