Abstract: An indoor unit for an air conditioner including a centrifugal fan. The centrifugal fan includes a main plate connectable to a rotation shaft of a motor, a plurality of blades, with one respective end to be bonded to the main plate and arrangeable at equal intervals from each other along a circumferential direction, a shroud, to be bonded to another respective end of the plurality of blades, to face the main plate, and a bell mouth arrangeable inside the shroud. An annular member arrangeable on an outer circumferential portion of the bell mouth with an inlet portion at the gap between the shroud and the bell mouth. The annular member including an annular flat plate portion spaced apart from and face the inlet portion, and a protrusion formed on an outer circumferential portion of a surface of the annular flat plate portion facing the shroud and being curved.

Abstract: A terminal apparatus and a method for communicating with a base station apparatus are provided. The method includes receiving Radio Resource Control (RRC) signaling and a first DCI format addressed to a Cell-Radio Network Temporary Identifier (C-RNTI); determining a first priority of a first uplink grant based on a priority field in the RRC signaling; and transmitting a first Physical Uplink Shared Channel (PUSCH) scheduled by the first uplink grant and a second PUSCH scheduled by a second uplink grant. The first uplink grant is a configured uplink grant notified by the RRC signaling. The second uplink grant is notified by the first DCI format.

Abstract: The instruction code including an instruction code stored in the area where the encrypted instruction code is stored in a non-rewritable format is authenticated using a specific key which is specific to the core where the instruction code is executed or an authenticated key by a specific key to perform an encryption processing for the input and output data between the core and the outside.

Abstract: In a processing apparatus having semiconductor integrated circuits, a first status monitoring circuit included in a first semiconductor integrated circuit is configured to instruct a plurality of second semiconductor integrated circuits to transmit status information indicating statuses of the plurality of second semiconductor integrated circuits. When a second status monitoring circuit included in each of the plurality of second semiconductor integrated circuits receives the instruction for transmission of the corresponding status information, the second status monitoring circuit transmits encrypted information in which the status information is encrypted to the first semiconductor integrated circuit.

Abstract: A bridge apparatus includes slave circuits connected to each other via a bus. Each of the slave circuits is connected to one of master apparatuses, function as a slave for the master apparatus connected thereto, and performs communication in accordance with a protocol in which the number of masters in a system is restricted. Addresses of memories are respectively set in the slave circuits, and the memories are connected to the master apparatuses to which the slave circuits are respectively connected. When a first master apparatus accesses a memory connected to a second master apparatus by specifying a first address of the memory, the bridge apparatus causes the first master apparatus and the second master apparatus to communicate via a first slave circuit, a second slave circuit in which an address corresponding to the first address is set, and the bus, based on the addresses of the memories.

Abstract: A semiconductor integrated circuit generates second boot code by encrypting first boot code, and transmits, based on route information indicating a delivery route of the second boot code, encrypted data including the second boot code to a first destination via a network. A different semiconductor integrated circuit is the first destination, and receives the encrypted data via the network and generates third boot code by decrypting the second boot code.

Abstract: A bridge apparatus includes slave circuits connected to each other via a bus. Each of the slave circuits is connected to one of master apparatuses, function as a slave for the master apparatus connected thereto, and performs communication in accordance with a protocol in which the number of masters in a system is restricted. Addresses of memories are respectively set in the slave circuits, and the memories are connected to the master apparatuses to which the slave circuits are respectively connected. When a first master apparatus accesses a memory connected to a second master apparatus by specifying a first address of the memory, the bridge apparatus causes the first master apparatus and the second master apparatus to communicate via a first slave circuit, a second slave circuit in which an address corresponding to the first address is set, and the bus, based on the addresses of the memories.

Abstract: Processing by an information processing system is speeded up. A first semiconductor integrated circuit designates a first address of a memory connected to a second semiconductor integrated circuit that is a data transmission destination, based on first memory map information in which addresses of memories respectively used by the semiconductor integrated circuits are defined, converts the first address to a second address of the memory defined in second memory map information referred to by the data transmission destination, and outputs the second address and transmission data by using a PCIe interface. A switch transfers the second address and the transmission data to the data transmission destination by using PCIe interfaces. The data transmission destination receives the second address and the transmission data by using a PCIe interface and writes the transmission data into the reception buffer region of the memory corresponding to the second address.

Abstract: In a processing apparatus having semiconductor integrated circuits, a first status monitoring circuit included in a first semiconductor integrated circuit is configured to instruct a plurality of second semiconductor integrated circuits to transmit status information indicating statuses of the plurality of second semiconductor integrated circuits. When a second status monitoring circuit included in each of the plurality of second semiconductor integrated circuits receives the instruction for transmission of the corresponding status information, the second status monitoring circuit transmits encrypted information in which the status information is encrypted to the first semiconductor integrated circuit.

Abstract: The instruction code including an instruction code stored in the area where the encrypted instruction code is stored in a non-rewritable format is authenticated using a specific key which is specific to the core where the instruction code is executed or an authenticated key by a specific key to perform an encryption processing for the input and output data between the core and the outside.

Abstract: The instruction code including an instruction code stored in the area where the encrypted instruction code is stored in a non-rewritable format is authenticated using a specific key which is specific to the core where the instruction code is executed or an authenticated key by a specific key to perform an encryption processing for the input and output data between the core and the outside.

Abstract: A vehicle drive assistance system is provided, which includes one or more processors configured to execute a general driver model learning engine configured to build a general driver model to be applied to a plurality of drivers based on driving data of the drivers, an individual driver model learning engine configured to build an individual driver model unique to a specific driver based on driving data of the driver, and an on-board controller provided in a vehicle operated by the driver. The individual driver model learning engine includes a vehicle control updating program configured to cause the on-board controller to update vehicle control processing based on the general and individual driver models. The vehicle control updating program acquires the driver models and, according to a given condition, determines a driver model based on which the vehicle control processing is updated, between the general and individual driver models.

Abstract: A system for planning operation of a power plant capable of a first mode driving a power generator using a turbine and a second mode not driving the power generator using the turbine over a predetermined period. A determination unit determines whether a predicted power-selling price is higher than a power generation cost; and a planning unit calculates a loss index of the first and second modes in a case where the predicted selling price is equal to the generation cost or less within the predetermined period and formulates a plan to operate the power plant in a mode having a smaller loss index. The loss index of the first mode includes a power-selling loss that is a difference between the predicted selling price and the generation cost, and the loss index of the second mode includes a loss that is caused by not driving the power generator.

Abstract: A method for manufacturing an electronic component, and a device for manufacturing the electronic component, which can easily achieve alignment by inserting multilayer chips into cavities formed in a pallet, and form external electrodes with a high degree of dimensional accuracy. A plurality of multilayer chips each composed of a laminated body with a plurality of ceramic layers and a plurality of internal electrode layers is inserted into each of a plurality of cavities formed in a pallet, and the plurality of multilayer chips is aligned by moving each of the plurality of multilayer chips to one of inner wall surfaces forming the cavity. A conductive ink is applied onto ends of the plurality of aligned multilayer chips, including the upper surface of the pallet, and the conductive ink applied is dried to form external electrodes on the plurality of multilayer chips.

Abstract: Processing by an information processing system is speeded up. A first semiconductor integrated circuit designates a first address of a memory connected to a second semiconductor integrated circuit that is a data transmission destination, based on first memory map information in which addresses of memories respectively used by the semiconductor integrated circuits are defined, converts the first address to a second address of the memory defined in second memory map information referred to by the data transmission destination, and outputs the second address and transmission data by using a PCIe interface. A switch transfers the second address and the transmission data to the data transmission destination by using PCIe interfaces. The data transmission destination receives the second address and the transmission data by using a PCIe interface and writes the transmission data into the reception buffer region of the memory corresponding to the second address.

Abstract: The instruction code including an instruction code stored in the area where the encrypted instruction code is stored in a non-rewritable format is authenticated using a specific key which is specific to the core where the instruction code is executed or an authenticated key by a specific key to perform an encryption processing for the input and output data between the core and the outside.

Abstract: A semiconductor integrated circuit includes a bus signal line and a test signal line arranged adjacent to the bus signal line. The semiconductor integrated circuit has a system mode, which is an operation mode that uses the bus signal line, and a scan mode, which is an operation mode that uses the test signal line. The semiconductor integrated circuit fixes the logic level of the test signal line adjacent to the bus signal line in the system mode that uses the bus signal line. The semiconductor integrated circuit fixes the logic level of the bus signal line adjacent to the test signal line in the scan mode that uses the test signal line.

Abstract: A semiconductor integrated circuit generates second boot code by encrypting first boot code, and transmits, based on route information indicating a delivery route of the second boot code, encrypted data including the second boot code to a first destination via a network. A different semiconductor integrated circuit is the first destination, and receives the encrypted data via the network and generates third boot code by decrypting the second boot code.

Abstract: The instruction code including an instruction code stored in the area where the encrypted instruction code is stored in a non-rewritable format is authenticated using a specific key which is specific to the core where the instruction code is executed or an authenticated key by a specific key to perform an encryption processing for the input and output data between the core and the outside.

Abstract: The instruction code including an instruction code stored in the area where the encrypted instruction code is stored in a non-rewritable format is authenticated using a specific key which is specific to the core where the instruction code is executed or an authenticated key by a specific key to perform an encryption processing for the input and output data between the core and the outside.