Abstract: When entering an idling state, a master unit M transmits an optical signal for polling addressed to each slave unit S-1 to S-n. The slave unit S-n located at the lowest rank of a direct chain constituted by S-1 to S-n, when receiving the optical signal for polling for the self unit, responds by transmitting an optical signal representing a phase correction request signal to the other slave units. The slave units S-1 to S-(n?1) respond to the phase correction request signal, and initialize each clock signal to synchronize with the clock signal of the slave unit S-n at the lowest rank.

Abstract: A network system (10) comprises a master device (5) and a plurality of slave devices (1, 2, 3), and those devices are serially connected to one another in such a way that the master device (5) comes to the most upstream side, thereby configuring an optical multidrop network which ensures data transmission and reception by optical communications among contiguous devices. Each of the slave devices (1, 2, 3) self-controls so as to be in such a state as not to receive data from any slave device on the downstream side when starting an operation, and the master device (5) controls the individual slave devices (1, 2, 3) sequentially from the upstream side to the downstream side in such a way that each slave device is capable of receiving data from a downstream side slave device.

Abstract: A memory device, performs fast data renewal and erasure, and is not easily degraded. In the memory area of a flash memory, each block is divided into physical pages and each physical pages is divided into logical pages. A redundancy portion is provided for each physical page. When supplied with to-be-written data and the logical address of a write destination, a CPU writes this data in an empty logical page and allocates the supplied logical address to this logical page. An old data flag in the redundancy portion in that physical page which includes a logical page having old data stored therein is changed in such a way as to indicate that data in this logical page is invalid. New data writing is done in that logical page to which a logical address is not allocated. At the time of flash-erasing a block, data which is stored in that logical page which is indicated by the old data flag is not transferred.

Abstract: When entering an idling state, a master unit M transmits an optical signal for polling addressed to each slave unit S-1 to S-n. The slave unit S-n located at the lowest rank of a direct chain constituted by S-1 to S-n, when receiving the optical signal for polling for the self unit, responds by transmitting an optical signal representing a phase correction request signal to the other slave units. The slave units S-1 to S-(n?1) respond to the phase correction request signal, and initialize each clock signal to synchronize with the clock signal of the slave unit S-n at the lowest rank.

Abstract: Disclosed are a memory device, which performs fast data renewal and erasure, and a memory device which is not easily degraded. In the memory area of a flash memory (11), each block is divided into physical pages and each physical pages is divided into logical pages. A redundancy portion is provided for each physical page. When supplied with to-be-written data and the logical address of a write destination, a CPU (121) writes this data in an empty logical page and allocates the supplied logical address to this logical page. An old data flag in the redundancy portion in that physical page which includes a logical page having old data stored therein is changed in such a way as to indicate that data in this logical page is invalid. New data writing is done in that logical page to which a logical address is not allocated. At the time of flash-erasing a block, data which is stored in that logical page which is indicated by the old data flag is not transferred.

Abstract: A storage device (10) has a flash memory (11), a controller (16) and a second ROM (15). In the flash memory (11), a data key is stored, which is a key unique to each storage device (10). In the second ROM (15), a system key is stored which is an encrypting key common to storage devices (10). The controller (16), when writing data, encrypts the data with the data and system keys and writes the encrypted data in the flash memory (11), and when reading data, decrypts the data with the data and system keys to output the decrypted data. The data key may be encrypted with the system key. In this case, when to write data, the controller (16) may decrypt the data key with the system key, and encrypt data with the decrypted key, and when to read data, the controller may decrypt the data key with the system key, and decrypt the encrypted data with the decrypted data key.

Abstract: A method, apparatus and system for controlling the reading and writing of flash memories including a write control section, a plurality of read enable control signal lines and a read control section. The write control section configured to supply a write command, a write head address and first data to each of the flash memories through a bus at a predetermined timing to cause one of the flash memories to perform a write mode for writing sequentially first data from a memory address of a corresponding one of the flash memories which is accessed by the write head address in response to the write command, the write head address and first data being supplied at a predetermined timing without fetching any external signal within a first time period. The plurality of read enable control signal lines connected to the plurality of flash memories, respectively, to assign individually a plurality of read enable control signals to the flash memories via the signal lines.

Abstract: An empty block table is constructed by 64 words.times.8 bits and has 512 memory positions 000H(A0) to IFFH(A511) one-to-one corresponding to 512 blocks BL0 to BL511 within a flash memory FMi. Empty data [a] of 1 bit is stored to each memory position (Aj). This empty data has value "1" when a block BLj corresponding to this memory position (Aj) is in an empty state at present. The empty data also has value "0" when no block BLj corresponding to this memory position (Aj) is in the empty state at present (when data are included in this block).