Patents by Inventor Seiji Ichikawa
Seiji Ichikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240069223Abstract: A radiation imaging device according to one embodiment comprises a radiation detection panel, a base substrate having a support surface configured to support the radiation detection panel, and a housing, wherein: the housing has a top wall and a bottom wall, the base substrate has a protruding portion which protrudes further outward than the radiation detection panel when seen in a direction orthogonal to the support surface, a first extending portion is provided to the support surface of the protruding portion, a second extending portion is provided to a back surface of the protruding portion, the second extending portion being disposed at a position which it faces the first extending portion with the protruding portion interposed therebetween, and the base substrate is supported on the top wall via the first extending portion and is supported on the bottom wall via the second extending portion.Type: ApplicationFiled: November 8, 2023Publication date: February 29, 2024Applicant: HAMAMATSU PHOTONICS K.K.Inventors: Ryuji KYUSHIMA, Kazuki FUJITA, Junichi SAWADA, Takao ARITAKE, Minoru ICHIKAWA, Haruyoshi OKADA, Seiji FUKAMIZU, Shuhei NAMBA
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Patent number: 7851884Abstract: A FET exhibiting excellent uniformity and productivity and having a low noise figure and high associated gain as high-frequency performance, a semiconductor chip having this FET and a semiconductor device having the semiconductor chip. The FET includes a GaAs substrate on which are built up an i-type GaAs layer, an i-type InGaAs two-dimensional electron gas layer and an n-type AlGaAs electron supply layer. A gate electrode is provided on and in linear Schottky contact with the n-type AlGaAs electron supply layer. A n-type InGaP etching stop layer and then an n-type GaAs contact layer at the same lateral position are built up on the n-type AlGaAs electron supply layer, these being spaced away from both sides of the gate electrode. A source electrode and a drain electrode are provided on the n-type GaAs contact layer and are spaced away from edges of the contact layer as electrodes that make band-shaped ohmic contact.Type: GrantFiled: September 24, 2008Date of Patent: December 14, 2010Assignee: Renesas Electronics CorporationInventors: Shuji Asai, Akira Fujihara, Makoto Matsunoshita, Naoki Sakura, Seiji Ichikawa
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Publication number: 20090078966Abstract: A FET exhibiting excellent uniformity and productivity and having a low noise figure and high associated gain as high-frequency performance, a semiconductor chip having this FET and a semiconductor device having the semiconductor chip. The FET includes a GaAs substrate on which are built up an i-type GaAs layer, an i-type InGaAs two-dimensional electron gas layer and an n-type AlGaAs electron supply layer. A gate electrode is provided on and in linear Schottky contact with the n-type AlGaAs electron supply layer. A n-type InGaP etching stop layer and then an n-type GaAs contact layer at the same lateral position are built up on the n-type AlGaAs electron supply layer, these being spaced away from both sides of the gate electrode. A source electrode and a drain electrode are provided on the n-type GaAs contact layer and are spaced away from edges of the contact layer as electrodes that make band-shaped ohmic contact.Type: ApplicationFiled: September 24, 2008Publication date: March 26, 2009Applicant: NEC Electronics CorporationInventors: Shuji Asai, Akira Fujihara, Makoto Matsunoshita, Naoki Sakura, Seiji Ichikawa
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Patent number: 6884210Abstract: It is an object of the present invention to realize a small and light blood pump that can control thrombosis and moreover, endure a prolonged use.Type: GrantFiled: June 12, 2002Date of Patent: April 26, 2005Assignees: Miwatec Incorporated, Baylor College of MedicineInventors: Yukihiko Nose, Seiji Ichikawa, Toshiyuki Shinohara
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Publication number: 20030233021Abstract: It is an object of the present invention to realize a small and light blood pump that can control thrombosis and moreover, endure a prolonged use.Type: ApplicationFiled: June 12, 2002Publication date: December 18, 2003Applicants: Miwatec Incorporated, Baylor College of MedicineInventors: Yukihiko Nose, Seiji Ichikawa, Toshiyuki Shinohara
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Patent number: 6467666Abstract: A method of producing a semiconductor device of the present invention is applicable to a multilayer wafer for leadless chip carrier packages and breaks it on a package basis. The method begins with a step of forming a generally V-shaped groove in one major surfaces of the wafer in the direction of thickness of the wafer. A weak, cleaving portion is formed in the other major surface of the wafer in alignment with the groove. A cleaving force is exerted on the wafer to thereby form a break in the cleaving portion, so that the wafer is caused to break from the groove toward the cleaving portion in the direction of thickness of the wafer. The cleaving portion may be replaced with a strong, non-cleaving portion, in which case the break is formed in the interface between the non-cleaving portion and the wafer due to a difference in cleaving force.Type: GrantFiled: May 30, 2001Date of Patent: October 22, 2002Assignee: NEC CorporationInventors: Seiji Ichikawa, Tatsuo Tokue, Nobuo Nagano, Fumie Ogihara, Taku Sato
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Publication number: 20010048014Abstract: A method of producing a semiconductor device of the present invention is applicable to a multilayer wafer for leadless chip carrier packages and breaks it on a package basis. The method begins with a step of forming a generally V-shaped groove in one major surfaces of the wafer in the direction of thickness of the wafer. A weak, cleaving portion is formed in the other major surface of the wafer in alignment with the groove. A cleaving force is exerted on the wafer to thereby form a break in the cleaving portion, so that the wafer is caused to break from the groove toward the cleaving portion in the direction of thickness of the wafer. The cleaving portion may be replaced with a strong, non-cleaving portion, in which case the break is formed in the interface between the non-cleaving portion and the wafer due to a difference in cleaving force.Type: ApplicationFiled: May 30, 2001Publication date: December 6, 2001Applicant: NEC CorporationInventors: Seiji Ichikawa, Tatsuo Tokue, Nobuo Nagano, Fumie Ogihara, Taku Sato
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Patent number: 6319753Abstract: A semiconductor device having lead terminals bent in a J-shape is disclosed. A radiating plate having a recess formed on an outer peripheral portion thereof is exposed to a lower face of a resin member and free ends of outer portions of the lead terminals are positioned in the recess of the radiating plate. The free ends of the outer portions of the lead terminals and the recess of the radiating plate are isolated from each other by projections of the resin member. Since the radiating plate is exposed to the lower face of the resin member, the heat radiating property is high whereas the radiating plate and the lead terminals are not short-circuited to each other at all.Type: GrantFiled: October 14, 1999Date of Patent: November 20, 2001Assignee: NEC CorporationInventors: Seiji Ichikawa, Takeshi Umemoto, Toshiaki Nishibe, Kazunari Sato, Kunihiko Tsubota, Masato Suga, Yoshikazu Nishimura, Keita Okahira, Tatsuya Miya, Toru Kitakoga, Kazuhiro Tahara
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Patent number: 6242797Abstract: A semiconductor device having a pellet mounted on a radiating plate thereof is disclosed. The radiating plate is formed in such a shape that a central portion thereof is positioned higher than both end portions thereof. A pellet is mounted on a lower face of the central portion of the radiating plate, and an upper face of the central portion of the radiating plate is exposed to the top of a resin member. Since the upper face of the central portion of the radiating plate which has the pellet mounted on the lower face thereof is exposed from the resin member, heat generated by the pellet can be radiated efficiently.Type: GrantFiled: April 13, 1998Date of Patent: June 5, 2001Assignee: NEC CorporationInventors: Seiji Ichikawa, Takeshi Umemoto, Toshiaki Nishibe, Kazunari Sato, Kunihiko Tsubota, Masato Suga, Yoshikazu Nishimura, Keita Okahira, Tatsuya Miya, Toru Kitakoga, Kazuhiro Tahara
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Patent number: 6177720Abstract: A semiconductor device is disclosed wherein a pair of radiating terminals and a plurality of lead terminals are formed from a single lead frame. A hole or holes in each radiating terminal are formed with an equal width and in an equal pitch to those of gaps between the lead terminals, and the opposite sides of each hole of the radiating terminal are connected to each other by a support element. The support elements of the radiating terminals and support elements which interconnect the lead terminals are formed with an equal length and in an equal pitch to allow the support elements to be cut away by a plurality of punches which are arranged in an equal pitch and have an equal width.Type: GrantFiled: November 12, 1999Date of Patent: January 23, 2001Assignee: NEC CorporationInventors: Seiji Ichikawa, Takeshi Umemoto, Toshiaki Nishibe, Kazunari Sato, Kunihiko Tsubota, Masato Suga, Yoshikazu Nishimura, Keita Okahira, Tatsuya Miya, Toru Kitakoga, Kazuhiro Tahara
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Patent number: 6175150Abstract: A plastic-encapsulated semiconductor device is provided, which is capable of efficient heat dissipation without upsizing while preventing the moisture from reaching an IC chip. This device is comprised of an electrically-conductive island having a chip-mounting area, an IC chip fixed on the chip-mounting area of the island, leads electrically connected to bonding pads of the chip through bonding wires, a plastic package for encapsulating the island, the chip, the bonding wires, and inner parts of the leads. The package has an approximately flat bottom face. Outer parts of the leads are protruded from the package and are located in approximately a same plane as the bottom face of the package. The island has an exposition part exposed from the package at a location excluding the chip-mounting area. A lower face of the exposition part of the island is located in approximately a same plane as the bottom face of the package. The chip and the chip-mounting area of the island are entirely buried in the package.Type: GrantFiled: April 17, 1998Date of Patent: January 16, 2001Assignee: NEC CorporationInventors: Seiji Ichikawa, Takeshi Umemoto, Toshiaki Nishibe, Kazunari Sato, Kunihiko Tubota, Masato Suga, Yoshikazu Nishimura, Keita Okahira, Tatsuya Miya, Tooru Kitakoga, Kazuhiro Tahara
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Patent number: 6165818Abstract: A semiconductor device is disclosed wherein a pair of radiating terminals and a plurality of lead terminals are formed from a single lead frame. A hole or holes in each radiating terminal are formed with an equal width and in an equal pitch to those of gaps between the lead terminals, and the opposite sides of each hole of the radiating terminal are connected to each other by a support element. The support elements of the radiating terminals and support elements which interconnect the lead terminals are formed with an equal length and in an equal pitch to allow the support elements to be cut away by a plurality of punches which are arranged in an equal pitch and have an equal width.Type: GrantFiled: May 7, 1998Date of Patent: December 26, 2000Assignee: NEC CorporationInventors: Seiji Ichikawa, Takeshi Umemoto, Toshiaki Nishibe, Kazunari Sato, Kunihiko Tsubota, Masato Suga, Yoshikazu Nishimura, Keita Okahira, Tatsuya Miya, Toru Kitakoga, Kazuhiro Tahara
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Patent number: 6150715Abstract: A semiconductor device of the present invention comprises a semiconductor pellet, a radiation plate mounted with the semiconductor pellet, a plurality of lead terminals electrically connected with the semiconductor pellet, and a resin member for encapsulating the above items. The resin member has a first surface and a second surface, and the radiation plate has a first portion exposed to the outside from the first surface of the resin member and a second portion exposed to the outside from the second surface of the resin member.Type: GrantFiled: July 28, 1998Date of Patent: November 21, 2000Assignee: NEC CorporationInventors: Seiji Ichikawa, Takeshi Umemoto, Kazunari Sato, Kunihiko Tsubota, Yoshikazu Nishimura, Toshiaki Nishibe, Kazuhiro Tahara, Masato Suga, Toru Kitakoga, Tatsuya Miya, Keita Okahira
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Patent number: 6104086Abstract: A semiconductor device having lead terminals bent in a J-shape is disclosed. A radiating plate having a recess formed on an outer peripheral portion thereof is exposed to a lower face of a resin member and free ends of outer portions of the lead terminals are positioned in the recess of the radiating plate. The free ends of the outer portions of the lead terminals and the recess of the radiating plate are isolated from each other by projections of the resin member. Since the radiating plate is exposed to the lower face of the resin member, the heat radiating property is high whereas the radiating plate and the lead terminals are not short-circuited to each other at all.Type: GrantFiled: April 13, 1998Date of Patent: August 15, 2000Assignee: NEC CorporationInventors: Seiji Ichikawa, Takeshi Umemoto, Toshiaki Nishibe, Kazunari Sato, Kunihiko Tsubota, Masato Suga, Yoshikazu Nishimura, Keita Okahira, Tatsuya Miya, Toru Kitakoga, Kazuhiro Tahara
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Patent number: 6011303Abstract: An electronic component includes a substrate portion, a bank portion, a plurality of lead members, an anchor hole, and at least a pair of notches. A chip is supported on the substrate portion. The bank portion is formed on a periphery of the substrate portion to surround the chip. The plurality of lead members are made of conductive strip pieces, and each lead member has an inner lead electrically connected to the chip and an outer lead extending to an outside. The substrate portion and the bank portion are integrally molded with a resin to include the lead members, so that the inner and outer leads are fixed to a connecting portion between the substrate portion and the bank portion. The anchor hole is formed in a portion where each of the lead members is in contact with the bank portion, and is filled with a resin. The pair of notches are formed in two ends of each of the lead members to sandwich the anchor hole.Type: GrantFiled: November 26, 1997Date of Patent: January 4, 2000Assignee: NEC CorporationInventors: Junichi Tanaka, Seiji Ichikawa, Tomoaki Hirokawa, Tomoaki Kimura, Taku Sato, Kenji Watanabe, Kenji Utida, Masatoshi Ohara, Takeo Ogihara, Satoshi Murata, Tsutomu Kubota
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Patent number: 5970322Abstract: An ultrahigh-frequency electronic component has an ultrahigh-frequency chip encased in a molded-resin package. The ultrahigh-frequency electronic component includes a first sealing layer encasing the ultrahigh-frequency chip therein and a second sealing layer encasing the first sealing layer therein. The first sealing layer contains a number of voids or minute air bubbles therein which are effective in reducing the permittivity of the first sealing layer. A method of manufacturing the ultrahigh-frequency electronic component is also disclosed.Type: GrantFiled: January 8, 1998Date of Patent: October 19, 1999Assignee: NEC CorporationInventors: Seiji Ichikawa, Tomoaki Hirokawa, Tomoaki Kimura, Taku Sato, Junichi Tanaka, Kenji Uchida, Masatoshi Ohara, Takeo Ogihara, Satoshi Murata, Tsutomu Kubota
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Patent number: 5956574Abstract: In a lead frame flash removing method and apparatus, a lead frame is molded integrally with a case. After molding, abrasive agent-mixed water is sprayed to a surface of the lead frame where a flash is formed. The lead frame is dipped in an electrolytic solution and applying a DC voltage is applied across the lead frame and an electrode in the electrolytic solution, thereby electrolytically processing the lead frame. After the electrolytic process, an external force is applied to the surface of the lead frame, thereby removing the flash.Type: GrantFiled: February 28, 1997Date of Patent: September 21, 1999Assignee: NEC CorporationInventors: Seiji Ichikawa, Junichi Tanaka, Tomoaki Hirokawa, Taku Sato, Tomoaki Kimura, Satoshi Murata, Tsutomu Kubota, Takeo Ogihara, Kenji Uchida, Kenji Watanabe, Tsutomu Noguti
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Patent number: 5904501Abstract: A hollow package manufacturing method includes the adhesive spreading step, the adhesive applying step, and the cap adhering step. In the adhesive spreading step, an adhesive is spread on a circular table to a uniform thickness. In the adhesive applying step, an open end face of a cylindrical cap having a bottom is urged against the circular table to apply the adhesive to the cap. In the cap adhering step, the cap applied with the adhesive is adhered to a case. A hollow package manufacturing apparatus is also disclosed.Type: GrantFiled: March 26, 1997Date of Patent: May 18, 1999Assignee: NEC CorporationInventors: Masatoshi Ohara, Takeo Ogihara, Satoshi Murata, Kenji Uchida, Tsutomu Kubota, Seiji Ichikawa, Tomoaki Hirokawa, Tomoaki Kimura, Taku Sato, Junichi Tanaka
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Patent number: 5905301Abstract: A package of the present invention comprises a base molded integrally with a lead frame by resin, a chip mounted on the lead frame, and a cap made of resin, which covers the chip and is fixed to the base. The base includes a substrate portion sealing the lead frame therein, a frame-shaped bank portion formed at a periphery of an upper surface of said substrate portion, the bank portion having said lead frame interposed between it snd the substrate portion, and an anchor portion formed at a portion of the lead frame interposed between the substrate portion and the bank portion. The chip is mounted on a region of the lead frame surrounded by the bank portion. The cap is fixed to the bank portion.Type: GrantFiled: February 3, 1997Date of Patent: May 18, 1999Assignee: NEC CorporationInventors: Seiji Ichikawa, Tomoaki Hirokawa, Tomoaki Kimura, Junichi Tanaka, Taku Sato, Satoshi Murata, Tsutomu Kubota, Takeo Ogihara, Kenji Uchida
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Patent number: 5889232Abstract: An ultrahigh-frequency electronic component has an ultrahigh-frequency chip encased in a molded-resin package. The ultrahigh-frequency electronic component includes a first sealing layer encasing the ultrahigh-frequency chip therein and a second sealing layer encasing the first sealing layer therein. The first sealing layer contains a number of voids or minute air bubbles therein which are effective in reducing the permittivity of the first sealing layer. A method of manufacturing the ultrahigh-frequency electronic component is also disclosed.Type: GrantFiled: May 13, 1997Date of Patent: March 30, 1999Assignee: NEC CorporationInventors: Seiji Ichikawa, Tomoaki Hirokawa, Tomoaki Kimura, Taku Sato, Junichi Tanaka, Kenji Uchida, Masatoshi Ohara, Takeo Ogihara, Satoshi Murata, Tsutomu Kubota