Abstract: An internal device (1) is implanted in a living body (300). A control section (6) causes a communication section (5) to wirelessly transmit data corresponding to electroencephalogram signals of the living body (300) which are detected through a group of N (N is 2 or more) electrodes, to an external device (200). When the communication section (5) receives a designation signal designating a group of M electrode(s) (2a), M being smaller than N, the communication section (5) is caused to transmit data corresponding to electroencephalogram signals of the living body (300) which are detected through the group of M electrode(s) (2a), to the external device (200) in real time.

Abstract: A resistance device (100) includes a field-effect transistor (TN) and a voltage applying circuit (1). The voltage applying circuit (1) applies a control voltage (Vgs) between the gate and source of the field-effect transistor (TN) according to a temperature (T) to control a resistance value (R) between the drain and source of the field-effect transistor (TN). The control voltage (Vgs) is a voltage obtained by adding a correction voltage (Vc) to a reference voltage (Vgs0). The correction voltage (Vc) depends on the temperature (T) and is set to be zero at a first temperature (T1).

Abstract: An internal device of a brain-machine interface system includes: an electrode group including N electrodes, N being 2 or more; an amplification element group including N amplification elements; a communicator communicating with an external device; and a controller selectively executing one of: a normal operation mode in which electroencephalogram signals acquired through the N electrodes are supplied to the amplification element group in a manner that each of the N electrodes corresponds to a respective one of the N amplification elements, and N amplified electroencephalogram signals are transmitted; and a noise-reduction operation mode in which an electroencephalogram signal acquired through an M electrode of the electrode group is supplied to the amplification element group in a manner that each M electrode corresponds to respective plural ones of the amplification elements, and an M amplified electroencephalogram signal is transmitted, M being smaller than N.

Abstract: An internal device (1) is implanted in a living body (300). A control section (6) causes a communication section (5) to wirelessly transmit data corresponding to electroencephalogram signals of the living body (300) which are detected through a group of N (N is 2 or more) electrodes, to an external device (200). When the communication section (5) receives a designation signal designating a group of M electrode(s) (2a), M being smaller than N, the communication section (5) is caused to transmit data corresponding to electroencephalogram signals of the living body (300) which are detected through the group of M electrode(s) (2a), to the external device (200) in real time.

Abstract: An internal device of a brain-machine interface system includes: an electrode group including N electrodes, N being 2 or more; an amplification element group including N amplification elements; a communicator communicating with an external device; and a controller selectively executing one of: a normal operation mode in which electroencephalogram signals acquired through the N electrodes are supplied to the amplification element group in a manner that each of the N electrodes corresponds to a respective one of the N amplification elements, and N amplified electroencephalogram signals are transmitted; and a noise-reduction operation mode in which an electroencephalogram signal acquired through an M electrode of the electrode group is supplied to the amplification element group in a manner that each M electrode corresponds to respective plural ones of the amplification elements, and an M amplified electroencephalogram signal is transmitted, M being smaller than N.

Abstract: An Image sensing apparatus employing a multi-chip system and having a super-parallel circuit structure capable of performing processes such as image processing in real time. A first chip of a first of a first stage has first pixel circuits each having an optical sensor and first processing circuits and arranged in a matrix. A second chip of a second stage has second pixel circuits each having an analog memory for storing analog information from the preceding stage and second processing circuits and arranged in a matrix so as to correspond to the first pixel circuits. In each of the first and the second chip, each of the first and the second processing circuits receives an analog signal from another first and second processing circuit in the vicinity so as to perform first and second analog processing and performs circuit noise compensation by parallel calculation.

Abstract: An Image sensing apparatus employing a multi-chip system and having a super-parallel circuit structure capable of performing processes such as image processing in real time. A first chip of a first of a first stage has first pixel circuits each having an optical sensor and first processing circuits and arranged in a matrix. A second chip of a second stage has second pixel circuits each having an analog memory for storing analog information from the preceding stage and second processing circuits and arranged in a matrix so as to correspond to the first pixel circuits. In each of the first and the second chip, each of the first and the second processing circuits receives an analog signal from another first and second processing circuit in the vicinity so as to perform first and second analog processing and performs circuit noise compensation by parallel calculation.