Patents by Inventor Seiji Kogure

Seiji Kogure has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6727718
    Abstract: A ball grid array (BGA) electronic component package having a configuration which is capable of improving mounting efficiency as well as preventing footprints from breaking away at circuit-connecting portions of the electronic component package. The BGA package has reinforcing bumps formed in an area located outward of a predetermined area in which conventional circuit-connecting bumps are arranged. Therefore, even if a shock is applied to the BGA package at the outer or peripheral portion of the BGA package, which is most sensitive to such a shock, the shock is absorbed by the reinforcing bumps and reinforcing footprints which have no electrical connection with the circuitry of the electronic component package. Thus, the footprints formed on a mounting portion of the BGA package and those formed on the printed circuit board can be prevented from breaking away or being cracked.
    Type: Grant
    Filed: November 19, 2002
    Date of Patent: April 27, 2004
    Assignee: Fujistu Limited
    Inventors: Yasuhiro Ichihara, Seiji Kogure, Hiroshi Iimura, Fumio Arase
  • Publication number: 20030063448
    Abstract: There is provided a ball grid array (BGA) electronic component package having a configuration which is capable of improving mounting efficiency as well as preventing footprints from breaking away at circuit-connecting portions of the electronic component package. The BGA package has reinforcing bumps formed in an area located outward of a predetermined area in which conventional circuit-connecting bumps are arranged. Therefore, even if a shock is applied to the BGA package e.g. when a printed circuit board having the BGA package mounted thereon is carelessly dropped during the manufacturing work, at the outer or peripheral portion of the BGA package, which is most sensitive to such a shock, the shock is absorbed by the reinforcing bumps and reinforcing footprints which have no electrical connection with the circuitry of the electronic component package.
    Type: Application
    Filed: November 19, 2002
    Publication date: April 3, 2003
    Applicant: Fujitsu Limited
    Inventors: Yasuhiro Ichihara, Seiji Kogure, Hiroshi Iimura, Fumio Arase
  • Patent number: 6498307
    Abstract: A ball grid array (BGA) electronic component package having a configuration which is capable of improving mounting efficiency as well as preventing footprints from breaking away at circuit-connecting portions of the electronic component package. The BGA package has reinforcing bumps formed in an area located outward of a predetermined area in which conventional circuit-connecting bumps are arranged. Therefore, even if a shock is applied to the BGA package e.g. when a printed circuit board having the BGA package mounted thereon is carelessly dropped during the manufacturing work, at the outer or peripheral portion of the BGA package, which is most sensitive to such a shock, the shock is absorbed by the reinforcing bumps and reinforcing footprints which have no electrical connection with the circuitry of the electronic component package. Thus, the footprints formed on a mounting portion of the BGA package and those formed on the printed circuit board can be prevented from breaking away or being cracked.
    Type: Grant
    Filed: July 29, 1998
    Date of Patent: December 24, 2002
    Assignee: Fujitsu Limited
    Inventors: Yasuhiro Ichihara, Seiji Kogure, Hiroshi Iimura, Fumio Arase
  • Publication number: 20010030057
    Abstract: There is provided a ball grid array (BGA) electronic component package having a configuration which is capable of improving mounting efficiency as well as preventing footprints from breaking away at circuit-connecting portions of the electronic component package. The BGA package has reinforcing bumps formed in an area located outward of a predetermined area in which conventional circuit-connecting bumps are arranged. Therefore, even if a shock is applied to the BGA package e.g. when a printed circuit board having the BGA package mounted thereon is carelessly dropped during the manufacturing work, at the outer or peripheral portion of the BGA package, which is most sensitive to such a shock, the shock is absorbed by the reinforcing bumps and reinforcing footprints which have no electrical connection with the circuitry of the electronic component package.
    Type: Application
    Filed: July 29, 1998
    Publication date: October 18, 2001
    Applicant: FUJITSU LIMITED
    Inventors: YASUHIRO ICHIHARA, SEIJI KOGURE, HIROSHI IIMURA, FUMIO ARASE
  • Patent number: 5337467
    Abstract: A wire-bonded substrate assembly is made up of a substrate having a first surface and a second surface which is opposite to the first surface, and a plurality of elements mounted on the first and second surfaces of the substrate. The elements at least include resin encapsulated integrated circuit chips which are wire-bonded and encapsulated by a synthetic resin. A first one of the resin encapsulated integrated circuit chips is mounted at a first region on the first surface of the substrate, while a second one of the resin encapsulated integrated circuit chips is mounted at a second region on the second surface of the substrate. The second region is other than a region on the second surface opposite to the first region on the first surface.
    Type: Grant
    Filed: November 22, 1991
    Date of Patent: August 16, 1994
    Assignee: Fujitsu Limited
    Inventors: Seiji Kogure, Mamoru Niishiro
  • Patent number: 5182853
    Abstract: A resin encapsulating structure includes a substrate having a first region and a second region which surrounds the first region, first pads provided on the substrate in an outer periphery of the second region, an integrated circuit chip which is mounted on the substrate within the first region, second pads provided on the integrated circuit chip, interconnections formed across the first and second pads above the second region, and a resin which is formed on the substrate and covers the integrated circuit chip and the interconnections. The substrate includes one or a plurality of holes which penetrate the substrate and are located within the second region, and the holes provide an escape path for air cells which are generated in the resin particularly when the resin flows between the interconnections.
    Type: Grant
    Filed: October 31, 1991
    Date of Patent: February 2, 1993
    Assignee: Fujitsu Limited
    Inventors: Yasushi Kobayashi, Seiji Kogure