Patents by Inventor Seiji Kumagai
Seiji Kumagai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230011340Abstract: A receiver circuit includes an input terminal for receiving an input current signal, a transimpedance amplifier having an input node, the transimpedance amplifier converting a current signal input to the input node into a voltage signal, an inductor having a first terminal and a second terminal, and a bypass circuit. The first terminal is coupled to the input terminal and the second terminal is coupled to the input node. The bypass circuit includes a bias circuit supplying a bias voltage, a first variable resistor coupled between the first terminal and the bias circuit, a second variable resistor coupled between the second terminal and the bias circuit, and an impedance adjustment circuit including a resistor and a capacitor connected in parallel to the resistor, the impedance adjustment circuit connected in series to at least one of the first variable resistor and the second variable resistor.Type: ApplicationFiled: June 29, 2022Publication date: January 12, 2023Applicant: Sumitomo Electric Industries, Ltd.Inventors: Seiji KUMAGAI, Yoshiyuki SUGIMOTO, Keiji TANAKA
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Patent number: 11486760Abstract: A receiving circuit includes a first input terminal and a second input terminal, an input circuit that includes a first node, a second node, a first inductor, a second inductor, a first variable resistive element, and a second variable resistive element. The first variable resistive element is electrically connected between the first node and the second input terminal, and the second variable resistive element is electrically connected between the second node and the first input terminal. The receiving circuit further includes a differential amplifier configured to generate a differential voltage signal in accordance with a differential current signal. The receiving circuit still further includes a control circuit configured to perform detection of an amplitude of the differential voltage signal and change a resistance value of the first variable resistive element and a resistance value of the second variable resistive element based on a result of the detection.Type: GrantFiled: August 18, 2021Date of Patent: November 1, 2022Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Seiji Kumagai, Yoshiyuki Sugimoto, Keiji Tanaka
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Patent number: 11405111Abstract: A receiving circuit and an optical receiver including the receiving circuit are disclosed. The receiving circuit includes first and second input terminals, a FET, first and second TIA circuits, and a control circuit. The first and second input terminals each receive a current signal. The FET has first and second current terminals respectively connected to the first and second input terminals, and a control terminal. The first and second TIA circuits respectively are connected to the first and second current terminals, and convert the current signals to first and second voltage signals. The control circuit generates a control signal for application to the FET control terminal in accordance with a difference between the first and second voltage signals. The optical receiver includes the receiving circuit and each of first and second photodetectors for respectively supplying first and second current signals to the first and second input terminals of the receiver.Type: GrantFiled: November 24, 2020Date of Patent: August 2, 2022Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Yoshiyuki Sugimoto, Seiji Kumagai
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Patent number: 11394352Abstract: A transimpedance amplifier circuit for generating an output voltage in accordance with an input current includes an offset resistor, a common emitter inverting amplifier having a first input and a first output, the first input receiving the input current, an emitter follower having a second input and a second output, the second input being coupled to the first output through the offset resistor, the second output outputting the output voltage, a feedback resistor connected between the second output and the first input, a variable current source connected to a node between the offset resistor and the second input, the variable current source configured to provide an offset current to the offset resistor, the offset current having a current value varied in accordance with a control signal, and a control circuit configured to generate the control signal so that an average voltage of the first output approaches a preset voltage value.Type: GrantFiled: November 13, 2020Date of Patent: July 19, 2022Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Yoshiyuki Sugimoto, Keiji Tanaka, Seiji Kumagai
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Publication number: 20220057262Abstract: A receiving circuit includes a first input terminal and a second input terminal, an input circuit that includes a first node, a second node, a first inductor, a second inductor, a first variable resistive element, and a second variable resistive element. The first variable resistive element is electrically connected between the first node and the second input terminal, and the second variable resistive element is electrically connected between the second node and the first input terminal. The receiving circuit further includes a differential amplifier configured to generate a differential voltage signal in accordance with a differential current signal. The receiving circuit still further includes a control circuit configured to perform detection of an amplitude of the differential voltage signal and change a resistance value of the first variable resistive element and a resistance value of the second variable resistive element based on a result of the detection.Type: ApplicationFiled: August 18, 2021Publication date: February 24, 2022Inventors: Seiji KUMAGAI, Yoshiyuki SUGIMOTO, Keiji TANAKA
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Publication number: 20210167863Abstract: The first and second input terminals are configured to receive first and second current signal respectively. The first FET has a first current terminal electrically connected to the first input terminal, a second current terminal electrically connected to the second input terminal, and a first control terminal receiving a first control signal. The first TIA circuit has a first input node which is electrically connected to the first current terminal. The first TIA circuit converts a current signal received at the first input node to the first voltage signal. The second TIA circuit has a second input node which is electrically connected to the second current terminal. The second TIA circuit converts a current signal received at the second input node to the second voltage signal. The control circuit generates the first control signal in accordance with a difference between the first and second voltage signals.Type: ApplicationFiled: November 24, 2020Publication date: June 3, 2021Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Yoshiyuki SUGIMOTO, Seiji KUMAGAI
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Publication number: 20210159858Abstract: A transimpedance amplifier circuit for generating an output voltage in accordance with an input current includes an offset resistor, a common emitter inverting amplifier having a first input and a first output, the first input receiving the input current, an emitter follower having a second input and a second output, the second input being coupled to the first output through the offset resistor, the second output outputting the output voltage, a feedback resistor connected between the second output and the first input, a variable current source connected to a node between the offset resistor and the second input, the variable current source configured to provide an offset current to the offset resistor, the offset current having a current value varied in accordance with a control signal, and a control circuit configured to generate the control signal so that an average voltage of the first output approaches a preset voltage value.Type: ApplicationFiled: November 13, 2020Publication date: May 27, 2021Inventors: Yoshiyuki SUGIMOTO, Keiji TANAKA, Seiji KUMAGAI
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Patent number: 10436964Abstract: Provided is an inorganic polarizing plate having a wire grid structure including: a transparent substrate; and grid-shaped protrusions arranged on the transparent substrate at a pitch shorter than a wavelength of light in a use band, in which the grid-shaped-protrusion includes, in order from the transparent substrate side, a reflection layer and a reflection suppressing layer which includes a dielectric material and a non-dielectric material and of which a content of the non-dielectric material increases as a separation from the reflection layer increases. In addition, provided are a method of manufacturing the inorganic polarizing plate and an optical instrument including the inorganic polarizing plate.Type: GrantFiled: February 5, 2018Date of Patent: October 8, 2019Assignee: Dexerials CorporationInventors: Akio Takada, Seiji Kumagai, Hideto Sagawa, Takahiro Kimura, Kazuyuki Shibuya, Toshiaki Sugawara, Shigeshi Sakakibara, Yusuke Matsuno
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Publication number: 20180224589Abstract: Provided is an inorganic polarizing plate having a wire grid structure including: a transparent substrate; and grid-shaped protrusions arranged on the transparent substrate at a pitch shorter than a wavelength of light in a use band, in which the grid-shaped-protrusion includes, in order from the transparent substrate side, a reflection layer and a reflection suppressing layer which includes a dielectric material and a non-dielectric material and of which a content of the non-dielectric material increases as a separation from the reflection layer increases. In addition, provided are a method of manufacturing the inorganic polarizing plate and an optical instrument including the inorganic polarizing plate.Type: ApplicationFiled: February 5, 2018Publication date: August 9, 2018Applicant: Dexerials CorporationInventors: Akio Takada, Seiji Kumagai, Hideto Sagawa, Takahiro Kimura, Kazuyuki Shibuya, Toshiaki Sugawara, Shigeshi Sakakibara, Yusuke Matsuno
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Patent number: 8089716Abstract: Provided is a magnetic tape that includes a data band, including servo patterns, data, and a guard space. The servo patterns is formed along a longitudinal direction of the magnetic tape with an interval provided between each of the servo patterns, each of the servo patterns formed across a full width of the data band. The data is recorded between the servo patterns. The guard space is left between each of the servo patterns and the data.Type: GrantFiled: December 17, 2008Date of Patent: January 3, 2012Assignee: Sony CorporationInventors: Jun Takayama, Seiji Kumagai
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Publication number: 20090161249Abstract: Provided is a magnetic tape that includes a data band, including servo patterns, data, and a guard space. The servo patterns is formed along a longitudinal direction of the magnetic tape with an interval provided between each of the servo patterns, each of the servo patterns formed across a full width of the data band. The data is disposed between the servo patterns. The guard space is disposed between each of the servo patterns and the data.Type: ApplicationFiled: December 17, 2008Publication date: June 25, 2009Applicant: Sony CorporationInventors: Jun TAKAYAMA, Seiji Kumagai
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Publication number: 20070230090Abstract: A capacitor includes two sub capacitors and two connecting portions. The two sub capacitors respectively include a lower electrode provided on a substrate, a dielectric film provided on the lower electrode, and an upper electrode provided on the dielectric film, and the two connecting portions respectively connecting the lower electrode of one of the two sub capacitors and the upper electrode of the other sub capacitor of the two sub capacitors.Type: ApplicationFiled: March 20, 2007Publication date: October 4, 2007Applicant: EUDYNA DEVICES INC.Inventor: Seiji Kumagai
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Patent number: 6535364Abstract: A magnetic resistance element is provided that includes an upper magnetic layer, which is formed in contact with an anti-ferromagnetic layer, and at least two magnetic layers that are layered with tunnel barrier wall layers respectively inserted between the first magnetic layer and each of the at least two magnetic layers such that the magnetic resistance element has a combined resistance that corresponds to one of four predefined magnetic resistances and that can be changed to another of the four predefined magnetic resistances by applying a predefined recording magnetic field pattern to the magnetic resistance element.Type: GrantFiled: January 14, 2000Date of Patent: March 18, 2003Assignee: Sony CorporationInventors: Seiji Kumagai, Yoshito Ikeda, Terunobu Miyazaki, Yoshiyuki Fukumoto
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Patent number: 6519123Abstract: A magnetic tunneling element in which the tunnel current flows reliably to exhibit a stable magnetic tunneling effect. The magnetic tunneling element includes a first magnetic layer, a tunnel barrier layer formed on the first magnetic layer, and a second magnetic layer formed on the tunnel barrier layer. The tunnel barrier layer is a metal film oxidized by inductively coupled oxygen plasma and a second magnetic layer is formed on the tunnel barrier layer.Type: GrantFiled: September 9, 1999Date of Patent: February 11, 2003Assignee: Sony CorporationInventors: Junichi Sugawara, Eiji Nakashio, Seiji Kumagai, Yoshito Ikeda
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Patent number: 6452892Abstract: First and second magnetic layers are laminated though a tunnel barrier layer, wherein a region is formed in which change in a magnetic resistance ratio with respect to change in a voltage applied in such a manner that the second magnetic layer has a lower potential as compared with the potential of the first magnetic layer is smaller than change in a magnetic resistance ratio with respect to change in a voltage applied in such a manner that the second magnetic layer has a higher potential as compared with the potential of the first magnetic layer. Voltage is applied to the magnetic tunnel device in such a manner that the potential of the second magnetic layer is lower than that of the first magnetic layer so that dependency of the magnetic resistance ratio on the voltage is reduced. Thus, a stable tunnel current flows.Type: GrantFiled: May 1, 2000Date of Patent: September 17, 2002Assignee: Sony CorporationInventors: Seiji Kumagai, Junichi Honda, Yoshito Ikeda
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Patent number: 6365948Abstract: A magnetic tunneling effect device capable of displaying a so-called magnetic tunneling effect in stability, more specifically, a magnetic tunneling junction device in which a first magnetic metal layer and a second magnetic metal layer are connected together by ferromagnetic tunnel junction via an insulating layer and in which the conductance of the tunnel current is changed by the relative angle of magnetization of these magnetic metal layers. The ferromagnetic tunnel junction has a junction area of not larger than 1 10−9 m2. For reliably controlling the junction area of the ferromagnetic tunnel junction, the insulating layer is formed by a first insulating layer for ferromagnetic tunnel junction and a second insulating layer formed on the first insulating layer for controlling the junction area of the ferromagnetic tunnel junction.Type: GrantFiled: March 26, 1997Date of Patent: April 2, 2002Assignee: Sony CorporationInventors: Seiji Kumagai, Toshihiko Yaoi, Yoshito Ikeda
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Patent number: 6312840Abstract: A magnetic tunnelling element in which the tunnel current flows reliably in an insulating layer to exhibit a stable magnetic tunnelling effect. To this end, the magnetic tunnelling element at least includes a first magnetic layer, a tunnel barrier layer formed on the first magnetic layer and a second magnetic layer formed on the tunnel barrier layer. The tunnel current flows via the tunnel barrier layer between the first magnetic metal layer and the second magnetic metal layer. The surface of the first magnetic layer carrying the tunnel barrier layer has a surface roughness (Ra) of 0.3 nm or less.Type: GrantFiled: September 16, 1999Date of Patent: November 6, 2001Assignee: Sony CorporationInventors: Seiji Kumagai, Eiji Nakashio, Junichi Sugawara, Yoshito Ikeda
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Patent number: 6219213Abstract: The present invention provides a magnetic head which has a magnetic circuit of a reduced size to cope with a high density recording and a preferable recording/reproduction characteristic. The magnetic head according to the present invention has at least partially a non-magnetic body 7 and includes: a magnetic circuit block 6 constituted by magnetic bodies arranged to oppose each other via the non-magnetic body 7; and a magnetic tunnel element 1 attached to this magnetic circuit block 6 and having a first magnetic layer 2 and a second magnetic layer 4 which are layered via an insulation layer 3. In this magnetic head, a magnetic field from a magnetic recording medium is induced to the magnetic circuit block and the induced magnetic field changes a relative angle of magnetization of the first magnetic layer 2 and/or the second magnetic layer 4 with the other magnetic layer of the magnetic tunnel element 1.Type: GrantFiled: June 26, 1998Date of Patent: April 17, 2001Assignee: Sony CorporationInventors: Kazuo Goto, Seiji Kumagai
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Patent number: 6213650Abstract: A bonding method for effectively preventing once-adjusted members from positionally deviating is disclosed. In this method, when applied to a method of making an optical module in particular, a holding member such as a magnet which generates a magnetic force against a housing is attached to, and a relative position of an optical reflecting member once adjusted by the holding member is held. As a result of this configuration, the optical reflecting member is effectively prevented from positionally deviating.Type: GrantFiled: February 18, 1999Date of Patent: April 10, 2001Assignee: Sumitomo Electric Industries, Ltd.Inventors: Yutaka Moriyama, Sosaku Sawada, Seiji Kumagai
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Patent number: 6103406Abstract: A novel magnetic tunnel device capable of displaying a magnetic tunnelling effect in stability and with high sensitivity even to an external magnetic field of a weak intensity. The magnetic tunnel device 1 has a layered structure including a first magnetic layer 2, a granular layer 3 layered on the first magnetic layer 2 and a second magnetic layer 4 layered on the surface of the granular layer 3 opposite to its surface carrying the first magnetic layer 2. The granular layer 3 has a granular structure which is made up of a magnetic metal phase 7 and an insulating phase 8. The first magnetic layer 2 and/or the second magnetic layer 4 of the magnetic tunnel device is formed of a ferromagnetic material having soft magnetic properties. The current is supplied in the layering direction of the layered structure.Type: GrantFiled: June 4, 1998Date of Patent: August 15, 2000Assignee: Sony CorporationInventor: Seiji Kumagai