Abstract: A load on a wireless communication system is measured without monitoring communication in a network by acquiring a serving cell RSRP indicating a reception strength of a reference signal received from one cell of an LTE system, an RSRQ indicating a reception quality of the reference signal, and a non-serving cell RSRP indicating a reception strength of a reference signal received from another cell other than the one cell, that are measured within the one cell, and deriving, based on the serving cell RSRP, the RSRQ and the non-serving cell RSRP, an estimate value of at least any of a PRB utilization ratio in the one cell and a PRB average utilization ratio in the one cell and the other cell.

Abstract: It is desirable to measure a load on a wireless communication system without monitoring communication in a network. In view of this, an estimating apparatus is provided, the estimating apparatus including: a measurement result acquiring unit that acquires: a serving cell RSRP indicating a reception strength of a reference signal received from one cell of an LTE system; an RSRQ indicating a reception quality of the reference signal; and a nonserving cell RSRP indicating a reception strength of a reference signal received from another cell other than the one cell, that are measured within the one cell; and an estimate value deriving unit that derives, based on the serving cell RSRP, the RSRQ and the nonserving cell RSRP, an estimate value of at least any of: a PRB utilization ratio in the one cell; and a PRB average utilization ratio in the one cell and the other cell.

Abstract: A signal conversion circuit is used to convert a parallel signal to a serial signal and comprises a parallel input/serial output type of shift register having input terminals corresponding in number to at least n+k bits (n and k: integer), an inverting circuit and a timing circuit. The n-bit input parallel signal is applied to n successive input terminals of the shift register and k bit of the n-bit parallel signal is inverted by the inverting circuit to be applied to the remaining k input terminal of the shift register. The (n+k)-bit parallel signal loaded into the shift register is serially output at a predetermined rate by the timing circuit to provide a serial signal.