Abstract: A large-scale computer system including a plurality of nodes is controlled to improve its system performance without aggregating data in a single site. There is provided a computer system including a plurality of computers, wherein a processor: detects a trigger to calculate a control value for controlling a process to be performed by the computer; identifies a target computer for which an evaluation value is obtained; calculates the evaluation value of its own computer; obtains the evaluation value from the target computer; calculates a first point using at least one of the evaluation value of its own computer and the evaluation value of the target computer; obtains a second point from the target computer; calculates the control value using the first point and the second point; and controls the process performed by the computer based on the control value.

Abstract: A memory module includes: a first memory device that is volatile or non-volatile; a second memory device that is non-volatile; a third memory device that is non-volatile; and a controller that controls the first to third memory devices, wherein a capacity of the second memory device is larger than a capacity of the first memory device, and a capacity of the third memory device is larger than the capacity of the second memory device, a second upper limit value of the number of rewritings of the second memory device is larger than a third upper limit value of the number of rewritings of the third memory device, and a first upper limit value of the number of rewritings of the first memory device is larger than the second upper limit value of the number of rewritings of the second memory device, and the controller accesses the second memory device with reference to a first address translation table related to the second memory device stored in the first memory device, and accesses the third memory device with ref

Abstract: Disclosed is a nonvolatile memory control method in which a unit of erase and a unit of read are different from each other. The control method includes: allocating a physical address of the nonvolatile memory to a logical address in a predetermined unit; and controlling a size of the unit of erase in which a physical address allocated to a logical address is included according to a write access state with respect to the logical address in the predetermined unit.

Abstract: An information processing device includes a host and a memory subsystem. The host issues an identifier indicating a data erasable order and a data write command to the memory subsystem and includes an information processing circuit for processing the data. The memory subsystem includes a first memory and a control circuit for writing the data in the first memory. The first memory has a data erase unit size larger than a data write unit size. The control circuit classifies the data based on the identifier, writes the data belonging to a first group in a first simultaneous erase region, in which data can be simultaneously erased, in the first memory, and writes the data belonging to a second group different from the first group in a second simultaneous erase region, in which data can be simultaneously erased, in the first memory. Consequently, the performance and the life of a storage device can be improved, and costs of the storage device can be reduced.

Abstract: A large-scale computer system including a plurality of nodes is controlled to improve its system performance without aggregating data in a single site. There is provided a computer system including a plurality of computers, wherein a processor: detects a trigger to calculate a control value for controlling a process to be performed by the computer; identifies a target computer for which an evaluation value is obtained; calculates the evaluation value of its own computer; obtains the evaluation value from the target computer; calculates a first point using at least one of the evaluation value of its own computer and the evaluation value of the target computer; obtains a second point from the target computer; calculates the control value using the first point and the second point; and controls the process performed by the computer based on the control value.

Abstract: An object of the present invention is to realize a highly reliable long-life information processor capable of high-speed operation and easy to handle. The processor includes a semiconductor device comprising a nonvolatile memory device including a plurality of overwritable memory cells, and a control circuit device for controlling access to the nonvolatile memory device. The control circuit device sets assignments of second addresses to the nonvolatile memory device independently of first addresses externally supplied, such that the physical disposition of part of the memory cells used for writing of first data to be written externally supplied is one of the first to (N+1)th of every (N+1) memory cells (N: a natural number) at least in one direction.

Abstract: A memory module includes: a first memory device that is volatile or non-volatile; a second memory device that is non-volatile; a third memory device that is non-volatile; and a controller that controls the first to third memory devices, wherein a capacity of the second memory device is larger than a capacity of the first memory device, and a capacity of the third memory device is larger than the capacity of the second memory device, a second upper limit value of the number of rewritings of the second memory device is larger than a third upper limit value of the number of rewritings of the third memory device, and a first upper limit value of the number of rewritings of the first memory device is larger than the second upper limit value of the number of rewritings of the second memory device, and the controller accesses the second memory device with reference to a first address translation table related to the second memory device stored in the first memory device, and accesses the third memory device with ref

Abstract: An information processing apparatus including a memory subsystem connected to a host to perform arithmetic processing, where the host notifies a write request including data and a type of the data to the memory subsystem, and, based on a first memory, a second memory which has a size of a data erase unit, for erasing data, larger than a size of a write unit of the data and a data capacity larger than that of the first memory, and the type of the data, the memory subsystem writes random access data and data other than the random access data in different erase units of the second memory.

Abstract: An information processing device includes a host and a memory subsystem. The host issues an identifier indicating a data erasable order and a data write command to the memory subsystem and includes an information processing circuit for processing the data. The memory subsystem includes a first memory and a control circuit for writing the data in the first memory. The first memory has a data erase unit size larger than a data write unit size. The control circuit classifies the data based on the identifier, writes the data belonging to a first group in a first simultaneous erase region, in which data can be simultaneously erased, in the first memory, and writes the data belonging to a second group different from the first group in a second simultaneous erase region, in which data can be simultaneously erased, in the first memory. Consequently, the performance and the life of a storage device can be improved, and costs of the storage device can be reduced.

Abstract: An object of this invention is to provide a semiconductor memory device capable of increasing the read transfer rate by performing the read operation in parallel while suppressing the voltage drop when a large current is passed to a memory chain and reducing a chip area by reducing the number of peripheral circuits to feed power. A semiconductor memory device according to this invention includes upper and lower electrodes in a flat plate shape, first and second select transistors extending in first and second directions respectively, and a wire arranged between the first select transistor and the second select transistor and the wire and the lower electrode are configured to be electrically insulated from each other by turning off the first select transistor (see FIG. 2).

Abstract: A semiconductor device includes a non-volatile memory unit including a plurality of chain memory arrays CY, and a control circuit that controls an access to the non-volatile memory unit. The control circuit sets, as a write area, a plurality of chain memory arrays CY arranged in a manner adjacent to each other and sets, as a dummy chain memory array DCY, a chain memory array arranged in an adjacent manner in an outer periphery of the write area. The control circuit does not perform an erasing operation on the dummy chain memory array DCY during batch-erasure of the write area. In the batch-erasure of the write area, the dummy chain memory array DCY functions to reduce an influence of heat disturbance.

Abstract: A data archive system includes a data library apparatus and a server. The data library apparatus includes recording media having recording surfaces on both surfaces, a recording media storage unit for storing the recording media, a recording/reproducing unit for the surface for recording/reproducing the data on/from the surface of the recording media, a recording/reproducing unit for the rear surface for recording/reproducing the data on/from the rear surface, and a recording media transporting unit for transporting the recording media between the recording media storage units. The server includes a data configuration unit for allocating the data for recording on the surface and the rear surface of the recording media and a controller for controlling the data library apparatus. The data configuration unit of the server alternately allocates the recording data on the surface and the rear surface of the recording media different from each other.

Abstract: The non-volatile storage solid state drive (SSD) has non-volatile memory (NVM), random access memory (RAM) capable of being accessed at a higher speed than this NVM, and a control unit for controlling accesses to the NVM and to the RAM. The control unit stores in the NVM an address translation table that translates a logical address given to access this NVM to a physical address after dividing it into multiple tables, and stores in the RAM the multiple address translation tables-sub on RAM that have been divided into multiple tables.

Abstract: A storage controller controlling a plurality of semiconductor storage devices includes at least one first semiconductor storage device storing effective data, and at least one second semiconductor storage device not storing effective data. The storage controller includes a table for management of information identifying the second semiconductor storage device from the plurality of semiconductor storage devices, and a control unit accessing the first semiconductor storage device or the second semiconductor storage device based on an operation state of the first semiconductor storage device and the table, and dynamically changing the table according to the access.

Abstract: An information processing device includes a host and a memory subsystem. The host issues a write command or an erase command with tag information corresponding to data to the memory subsystem and includes an information processing circuit for processing the data. The memory subsystem includes a first memory, a second memory, and a memory subsystem control circuit. The first memory stores management information for managing the second memory. The second memory has a larger size of a data erase unit than a size of a data write unit and stores the data. The memory subsystem control circuit writes data on the same tag information in the same management unit and writes data on the different tag information in the different management unit, based on the management information in which n times of the data erase unit (“n” is a natural number) is a management unit.

Abstract: A semiconductor device including a nonvolatile memory cell realizes enhancement of reliability and convenience. The semiconductor device includes a nonvolatile memory unit that includes plural overwritable memory cells (CL), and a control circuit that controls access to the nonvolatile memory unit. The control circuit allocates one physical address to a chain memory array CY in the nonvolatile memory unit, for example. The control circuit performs writing to a memory cell (for example, CL0) that is apart of the chain memory array CY according to a first write command with respect to the physical address, and performs writing to a memory cell (for example, CL1) that is another part thereof according to a second write command with respect to the physical address.

Abstract: An object of this invention is to provide a semiconductor memory device capable of increasing the read transfer rate by performing the read operation in parallel while suppressing the voltage drop when a large current is passed to a memory chain and reducing a chip area by reducing the number of peripheral circuits to feed power. A semiconductor memory device according to this invention includes upper and lower electrodes in a flat plate shape, first and second select transistors extending in first and second directions respectively, and a wire arranged between the first select transistor and the second select transistor and the wire and the lower electrode are configured to be electrically insulated from each other by turning off the first select transistor (see FIG. 2).

Abstract: A control circuit of a semiconductor device (memory module) realizes long life and others by a mechanism that suppresses and smoothes variations in use of a memory by equalizing the sizes of data write and data erase with respect to a data write request and sequentially allocating and using addresses of the memory in data write to an overwritable non-volatile memory device without carrying out an overwriting operation even in the case of an overwrite request. The control circuit realizes data write by a set of two types of operations of (a) an operation of erasing data of a first address or an operation of setting a flag value to an invalid state and (b) an operation of writing data to a second address different from the first address or an operation of setting a flag value to a valid state.

Abstract: An information processor includes an information processing sub-system having information processing circuits and a memory sub-system performing data communication with the information processing sub-systems, wherein the memory sub-system has a first memory, a second memory, a third memory having reading and writing latencies longer than those of the first memory and the second memory, and a memory controller for controlling data transfer among the first memory, the second memory and the third memory; graph data is stored in the third memory; the memory controller analyzes data blocks serving as part of the graph data, and performs preloading operation repeatedly to transfer the data blocks to be required next for the execution of the processing from the third memory to the first memory or the second memory on the basis of the result of the analysis.

Abstract: A first objective is to reduce performance degradation of a semiconductor storage resulting from address translation. A second objective is to reduce an increase in the manufacturing cost of the semiconductor storage resulting from address translation. A third objective is to provide the semiconductor storage with high reliability. To accomplish the above objectives, a storage area of a nonvolatile memory included in the semiconductor storage is segmented into multiple blocks, and each of the blocks is segmented into multiple pages. Then, an erase count is controlled on a page basis (109), and address translation is controlled on a block basis (108).