Patents by Inventor Seiji Miyagawa

Seiji Miyagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11054783
    Abstract: An image reading device includes a marking part that applies a predetermined mark to a margin of a rear end of a document having passed through an image reading position, a mark erasing part that erases the predetermined mark when the document is discharged from a sheet discharge port, and an image data processing unit that determines whether the predetermined mark exists in image data of a document image read by an image reading unit and erases the image data of the document image when it is determined that the predetermined mark exists.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: July 6, 2021
    Assignee: KYOCERA Document Solutions Inc.
    Inventor: Seiji Miyagawa
  • Publication number: 20190204773
    Abstract: An image reading device includes a marking part that applies a predetermined mark to a margin of a rear end of a document having passed through an image reading position, a mark erasing part that erases the predetermined mark when the document is discharged from a sheet discharge port, and an image data processing unit that determines whether the predetermined mark exists in image data of a document image read by an image reading unit and erases the image data of the document image when it is determined that the predetermined mark exists.
    Type: Application
    Filed: December 27, 2018
    Publication date: July 4, 2019
    Inventor: Seiji Miyagawa
  • Publication number: 20160085736
    Abstract: A document browsing device causes a display portion to display a row specifying image which specifies one row in a page image, and detects a change in a gazing direction of a viewer. Further, when the gazing direction has shown a predetermined change along a row direction of character strings in the page image, the document browsing device updates a display state of the row specifying image on the display portion to a state to specify a row next to a row to be specified at a point of time of the satisfaction.
    Type: Application
    Filed: September 16, 2015
    Publication date: March 24, 2016
    Inventor: Seiji Miyagawa
  • Patent number: 9036224
    Abstract: In an image reading device, an interlock portion is configured to supply or cut off power supply voltage to a driving portion in association with opening/closing of a cover. An open/close detecting portion is configured to detect opening/closing of the cover. A control portion is configured to execute (a) a scan process of causing a reading portion to read a document image during movement of the reading portion from a first position to a second position, (b) a return process of returning the reading portion to the first position in the opposite direction, (c) a reading interruption process of stopping a scan process when an opened state of the cover is detected during the scan process, and executing a return process when a closed state of the cover is detected next time, and (d) the scan process again after the reading interruption process.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: May 19, 2015
    Assignee: Kyocera Document Solutions Inc.
    Inventor: Seiji Miyagawa
  • Publication number: 20140211278
    Abstract: In an image reading device, an interlock portion is configured to supply or cut off power supply voltage to a driving portion in association with opening/closing of a cover. An open/close detecting portion is configured to detect opening/closing of the cover. A control portion is configured to execute (a) a scan process of causing a reading portion to read a document image during movement of the reading portion from a first position to a second position, (b) a return process of returning the reading portion to the first position in the opposite direction, (c) a reading interruption process of stopping a scan process when an opened state of the cover is detected during the scan process, and executing a return process when a closed state of the cover is detected next time, and (d) the scan process again after the reading interruption process.
    Type: Application
    Filed: January 31, 2014
    Publication date: July 31, 2014
    Applicant: Kyocera Document Solutions Inc.
    Inventor: Seiji Miyagawa
  • Patent number: 8514460
    Abstract: Reference patterns disposed on a platen unit are read by optically scanning the reference patterns and stored in an image memory as pattern image data. An interval between the reference patterns, the interval being stored in advance, is compared with intervals between read images of the reference patterns to calculate correction scaling factors for scaling the intervals between the read images. Document image data read by scanning a document placed on the platen unit is multiplied by the calculated correction scaling factors to adjust magnification accuracy of an image of the document.
    Type: Grant
    Filed: September 10, 2009
    Date of Patent: August 20, 2013
    Assignee: KYOCERA Document Solutions Inc.
    Inventor: Seiji Miyagawa
  • Patent number: 8056042
    Abstract: An automatic delay adjusting method of a semiconductor integrated circuit includes placing a dummy wiring to a layout data and connecting the dummy wiring to a target wiring between a first cell and a second cell which is a timing violation occurs for the target wiring in the layout data. The dummy wiring connection includes replacing the dummy wiring with a dummy wiring cell having first and second pins corresponding to both ends of the dummy wiring, cutting the target wiring to generate first and second target wirings, connecting the first and second target wirings to the first and second pins, respectively, and replacing the dummy wiring cell with the dummy wiring to provide a wiring that is connected with the dummy wiring to the cut target wiring.
    Type: Grant
    Filed: June 18, 2008
    Date of Patent: November 8, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Seiji Miyagawa
  • Publication number: 20100157380
    Abstract: Reference patterns disposed on a platen unit are read by optically scanning the reference patterns and stored in an image memory as pattern image data. An interval between the reference patterns, the interval being stored in advance, is compared with intervals between read images of the reference patterns to calculate correction scaling factors for scaling the intervals between the read images. Document image data read by scanning a document placed on the platen unit is multiplied by the calculated correction scaling factors to adjust magnification accuracy of an image of the document.
    Type: Application
    Filed: September 10, 2009
    Publication date: June 24, 2010
    Applicant: Kyocera Mita Corporation
    Inventor: Seiji Miyagawa
  • Publication number: 20090007041
    Abstract: An automatic delay adjusting method of a semiconductor integrated circuit includes placing a dummy wiring to a layout data and connecting the dummy wiring to a target wiring between a first cell and a second cell which is a timing violation occurs for the target wiring in the layout data. The dummy wiring connection includes replacing the dummy wiring with a dummy wiring cell having first and second pins corresponding to both ends of the dummy wiring, cutting the target wiring to generate first and second target wirings, connecting the first and second target wirings to the first and second pins, respectively, and replacing the dummy wiring cell with the dummy wiring to provide a wiring that is connected with the dummy wiring to the cut target wiring.
    Type: Application
    Filed: June 18, 2008
    Publication date: January 1, 2009
    Applicant: NEC Electronics Corporation
    Inventor: Seiji Miyagawa
  • Patent number: 7451430
    Abstract: In a transistor model generating apparatus, a transistor region extracting section extracts a non-rectangular transistor region, in which a gate region is formed above a non-rectangular diffusion layer region, from a mask layout data of a semiconductor integrated circuit. A dividing section sets a division line extending in a direction of a gate length of a transistor to divide the non-rectangular transistor region into a plurality of rectangular transistor regions. A relating section relates the non-rectangular transistor region and the plurality of rectangular transistor regions with the mask layout data. A size calculating section calculates a size data of each of the plurality of rectangular transistor regions. A correction value calculating section calculates a correction value of a diffusion layer length dependency parameter to the plurality of rectangular transistor regions based on the size data.
    Type: Grant
    Filed: July 3, 2006
    Date of Patent: November 11, 2008
    Assignee: NEC Electronics Corporation
    Inventor: Seiji Miyagawa
  • Publication number: 20070001221
    Abstract: In a transistor model generating apparatus, a transistor region extracting section extracts a non-rectangular transistor region, in which a gate region is formed above a non-rectangular diffusion layer region, from a mask layout data of a semiconductor integrated circuit. A dividing section sets a division line extending in a direction of a gate length of a transistor to divide the non-rectangular transistor region into a plurality of rectangular transistor regions. A relating section relates the non-rectangular transistor region and the plurality of rectangular transistor regions with the mask layout data. A size calculating section calculates a size data of each of the plurality of rectangular transistor regions. A correction value calculating section calculates a correction value of a diffusion layer length dependency parameter to the plurality of rectangular transistor regions based on the size data.
    Type: Application
    Filed: July 3, 2006
    Publication date: January 4, 2007
    Inventor: Seiji Miyagawa
  • Patent number: 6949320
    Abstract: The preparation method of an exposure original plate according to the present invention includes a step of subdividing a pattern constituting an exposure original plate into a plurality of rectangular patterns, a step of extracting micro patterns having the size of a side smaller than a prescribed value from among the divided individual rectangular patterns, a step of forming a corrected micro pattern by increasing the size of the side of the extracted micro pattern perpendicular to the side making contact with an adjacent patter at least by the prescribed value, a step of forming a corrected adjacent pattern by retreating the side of the adjacent pattern making contact with the corrected micro pattern by the increased amount corresponding to the prescribed value, and a step of finding EB exposure data for the pattern including the corrected micro pattern and the corrected adjacent pattern, and carrying out EB exposure by the variable shaped beam exposure method based on the EB exposure data.
    Type: Grant
    Filed: April 22, 2003
    Date of Patent: September 27, 2005
    Assignee: NEC Electronics Corporation
    Inventor: Seiji Miyagawa
  • Publication number: 20030203287
    Abstract: The preparation method of an exposure original plate according to the present invention includes a step of subdividing a pattern constituting an exposure original plate into a plurality of rectangular patterns, a step of extracting micro patterns having the size of a side smaller than a prescribed value from among the divided individual rectangular patterns, a step of forming a corrected micro pattern by increasing the size of the side of the extracted micro pattern perpendicular to the side making contact with an adjacent patter at least by the prescribed value, a step of forming a corrected adjacent pattern by retreating the side of the adjacent pattern making contact with the corrected micro pattern by the increased amount corresponding to the prescribed value, and a step of finding EB exposure data for the pattern including the corrected micro pattern and the corrected adjacent pattern, and carrying out EB exposure by the variable shaped beam exposure method based on the EB exposure data.
    Type: Application
    Filed: April 22, 2003
    Publication date: October 30, 2003
    Applicant: NEC Electronics Corporation
    Inventor: Seiji Miyagawa
  • Patent number: 6519758
    Abstract: The present invention provides a method of checking exposure patterns with reference to checking data, and the exposure patterns having an overlapping region receiving double-exposures of electron beams which vary a width of an interconnection part across the overlapping region, wherein data for a width of the interconnection part across the overlapping region in the checking data are modified to vary the width of the interconnection part.
    Type: Grant
    Filed: December 20, 2000
    Date of Patent: February 11, 2003
    Assignee: NEC Corporation
    Inventor: Seiji Miyagawa
  • Publication number: 20010004765
    Abstract: The present invention provides a method of checking exposure patterns with reference to checking data, and the exposure patterns having an overlapping region receiving double-exposures of electron beams which vary a width of an interconnection part across the overlapping region, wherein data for a width of the interconnection part across the overlapping region in the checking data are modified to vary the width of the interconnection part.
    Type: Application
    Filed: December 20, 2000
    Publication date: June 21, 2001
    Applicant: NEC Corporation
    Inventor: Seiji Miyagawa
  • Patent number: 6033812
    Abstract: In a photomask manufacturing method, third data is generated by multiplying the size of second data by x. Synthetic data is generated by synthesizing first data and the third data using first connection data from the first data and second connection data from the third data. It is verified whether a combination of transistors and wirings in the synthetic data matches with a circuit on which the layout design is based. A portion in which an error is detected by the verification is corrected. First EB drawing pattern data is generated from the first data and first connection data of the corrected synthetic data. Second EB drawing pattern data is generated by multiplying the third data and second connection data of the corrected synthetic data by 1/x.
    Type: Grant
    Filed: May 27, 1999
    Date of Patent: March 7, 2000
    Assignee: NEC Corporation
    Inventor: Seiji Miyagawa