Patents by Inventor Seiji Ochi
Seiji Ochi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 5907161Abstract: A semiconductor device includes a III-V compound semiconductor layer including two or more Group III elements and containing dopant impurities, including a spontaneous superlattice, and having a stripe shape with two ends, and electrodes disposed on the ends of the stripe shaped semiconductor layer to form a resistor element. Because of the spontaneous superlattice, electrons are one-dimensionally confined within the III-V compound semiconductor layer, i.e., the electrons flow easier in the direction perpendicular to the periodic direction of the spontaneous superlattice than in the direction parallel to it, resulting in anisotropic electrical resistivity. Therefore, the orientation of the resistor element with respect to the periodic direction of the spontaneous superlattice becomes another factor in determining the resistance of the resistor element.Type: GrantFiled: February 2, 1998Date of Patent: May 25, 1999Assignee: Mitsubishi Denki KabushikikaishaInventors: Seiji Ochi, Tatuya Kimura
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Patent number: 5886360Abstract: A semiconductor device includes a semiconductor substrate; a semiconductor laminated structure including a first barrier layer, a conduction layer including a natural superlattice, and a second barrier layer, disposed on the semiconductor substrate. The first barrier layer, the conduction layer, and the second barrier layer produce heterojunctions that confine charge carriers within the conduction layer. The first barrier layer has steps at the surface contacting the conduction layer, the steps including, alternatingly arranged, a first crystal plane having a first orientation and a second crystal plane having a second orientation. The conduction layer includes first portions where the natural superlattice is ordered and second portions where the natural superlattice is disordered, the first and second portions being disposed on the first and second crystal planes, respectively. The degree of order in the conduction layer is higher in the first portions than in the second portions.Type: GrantFiled: June 14, 1996Date of Patent: March 23, 1999Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Seiji Ochi
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Patent number: 5818073Abstract: A semiconductor device includes a III-V compound semiconductor layer including two or more Group III elements and containing dopant impurities, including a spontaneous superlattice, and having a stripe shape with two ends, and electrodes disposed on the ends of the stripe shaped semiconductor layer to form a resistor element. Because of the spontaneous superlattice, electrons are one-dimensionally confined within the III-V compound semiconductor layer, i.e., the electrons flow easier in the direction perpendicular to the periodic direction of the spontaneous superlattice than in the direction parallel to it, resulting in anisotropic of electrical resistivity. Therefore, the orientation of the resistor element with respect to the periodic direction of the spontaneous superlattice becomes another factor in determining the resistance of the resistor element.Type: GrantFiled: September 29, 1995Date of Patent: October 6, 1998Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Seiji Ochi, Tatuya Kimura
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Patent number: 5804840Abstract: A method of fabricating a semiconductor device includes forming a stripe-shaped first insulating film on a semiconductor layer; using the first insulating film as a mask, etching the semiconductor layer to a depth to form a stripe-shaped ridge including a portion of the semiconductor layer left under the first insulating film; using the first insulating film as a mask, growing, by MOCVD, a high-resistance layer, selected from InAlAs and InAsGaAs, contacting both sides of the ridge structure, the high-resistance layer having a shallow donor concentration N.sub.SD, a shallow acceptor concentration N.sub.SA, and a deep donor concentration N.sub.DD in relationships of N.sub.SA >N.sub.SD and N.sub.SA -N.sub.SD <N.sub.DD ; removing the first insulating film; forming a second insulating film covering the high-resistance layer; and forming a surface electrode on the semiconductor layer at the ridge structure.Type: GrantFiled: April 19, 1996Date of Patent: September 8, 1998Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Seiji Ochi, Manabu Kato
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Patent number: 5602414Abstract: In a method for fabricating an infrared detector, initially, a CdHgTe layer of a first conductivity type is produced on a front surface of a semiconductor substrate, a plurality of spaced apart CdHgTe regions of a second conductivity type, opposite the first conductivity type, are produced at the surface of the first conductivity type CdHgTe layer, and part of the surface of the first conductivity type CdHgTe layer between the second conductivity type CdHgTe regions is selectively irradiated with a charged particle beam to evaporate Hg atoms from that part, whereby a CdHgTe separation region of the first conductivity type and having a Cd composition larger than that of the first conductivity type CdHgTe layer is produced penetrating through the first conductivity type CdHgTe layer and surrounding each of the second conductivity type CdHgTe regions. Therefore, a highly-integrated high-resolution infrared detector with no crosstalk between pixels is achieved.Type: GrantFiled: June 16, 1994Date of Patent: February 11, 1997Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kotaro Mitsui, Zenpei Kawazu, Kazuo Mizuguchi, Seiji Ochi, Yuji Ohkura, Norio Hayafuji, Hirotaka Kizuki, Mari Tsugami, Akihiro Takami, Manabu Katoh
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Patent number: 5490159Abstract: A visible light semiconductor laser includes a GaAs substrate having a surface making a first angle with a (100) surface toward the [011] direction. A semiconductor layer having a surface making a second angle smaller than the first angle with the (100) surface is disposed on a part of the first surface of the GaAs substrate. The semiconductor layer extends in the [011] direction and does not reach the opposite resonator facets of the laser. A first AlGaInP active layer is disposed on the the surface making the second angle with the (100) surface of the semiconductor layer, and the first active layer includes regularly ordered atoms. A second AlGaInP active layer is disposed on the first surface of the GaAs substrate. The second active layer includes disordered atoms and has a band gap energy larger than that of the first active layer. The second active layer serves as a window layer.Type: GrantFiled: October 5, 1994Date of Patent: February 6, 1996Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Seiji Ochi, Tatsuya Kimura
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Patent number: 5389798Abstract: A high-speed semiconductor device includes an emitter layer serving as an injection source of hot electrons and a collector barrier layer disposed between a base layer and a collector layer. The potential profile of the collector barrier layer gradually varies from a region in the vicinity of the boundary between the base layer and the collector barrier layer whereby reflection of electrons at the collector barrier layer is significantly reduced. Therefore, current density in the ON state of the device is increased without damaging the high speed characteristics of the device, and current density in the OFF state of the device is decreased, resulting in a high-performance and high-speed semiconductor device.Type: GrantFiled: October 1, 1992Date of Patent: February 14, 1995Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Seiji Ochi, Hirotaka Kizuki
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Patent number: 5248347Abstract: In a semiconductor device having a metal electrode on a crystalline semiconductor surface, the metal electrode includes first portions electrically and mechanically connected to the surface and second portions mechanically separated from the surface and having configurations that easily deform. These first and second portions are alternatingly arranged on the surface. Accordingly, stress applied to the semiconductor beneath the electrode is reduced and deformation of the semiconductor element due to thermal stress is prevented, thereby preventing deterioration of element characteristics.Type: GrantFiled: February 6, 1992Date of Patent: September 28, 1993Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Seiji Ochi