Abstract: An ESD protection element can have a high ESD protection characteristic which has a desired breakdown voltage and flows a large discharge current. A junction diode is formed by an N+ type buried layer having a proper impurity concentration and a P+ type buried layer. The P+ type buried layer is combined with a P+ type drawing layer to penetrate an N? type epitaxial layer and be connected to an anode element. An N+ type diffusion layer and a P+ typed diffusion layer connected to an surrounding the N+ type diffusion layer are formed in the N? epitaxial layer surrounded by the P+ type buried layer etc. The N+ type diffusion layer and P+ type diffusion layer are connected to a cathode electrode. An ESD protection element is formed by the PN junction diode and a parasitic PNP bipolar transistor which uses the P+ type diffusion layer as an emitted, the N? type epitaxial layer as the base, and the P+ type drawing layer etc. as the collector.

Abstract: An N type layer made of an N type epitaxial layer in which an N+ type drain layer etc are formed is surrounded by a P type drain isolation layer extending from the front surface of the N type epitaxial layer to an N+ type buried layer. A P type collector layer is formed in an N type layer made of the N type epitaxial layer surrounded by the P type drain isolation layer and a P type element isolation layer, extending from the front surface to the inside of the N type layer. A parasitic bipolar transistor that uses the first conductive type drain isolation layer as the emitter, the second conductive type N type layer as the base, and the collector layer as the collector is thus formed so as to flow a surge current into a ground line.

Abstract: An ESD protection element can have a high ESD protection characteristic which has a desired breakdown voltage and flows a large discharge current. A junction diode is formed by an N+ type buried layer having a proper impurity concentration and a P+ type buried layer. The P+ type buried layer is combined with a P+ type drawing layer to penetrate an N? type epitaxial layer and be connected to an anode element. An N+ type diffusion layer and a P+ typed diffusion layer connected to an surrounding the N+ type diffusion layer are formed in the N? epitaxial layer surrounded by the P+ type buried layer etc. The N+ type diffusion layer and P+ type diffusion layer are connected to a cathode electrode. An ESD protection element is formed by the PN junction diode and a parasitic PNP bipolar transistor which uses the P+ type diffusion layer as an emitted, the N? type epitaxial layer as the base, and the P+ type drawing layer etc. as the collector.

Abstract: An ESD protection element is formed by a PN junction diode including an N+ type buried layer having a proper impurity concentration and a P+ type buried layer and a parasitic PNP bipolar transistor which uses a P+ type drawing layer connected to a P+ type diffusion layer as the emitter, an N? type epitaxial layer as the base, and a P type semiconductor substrate as the collector. The P+ type buried layer is connected to an anode electrode, and the P+ type diffusion layer and an N+ type diffusion layer connected to and surrounding the P+ type diffusion layer are connected to a cathode electrode. When a large positive static electricity is applied to the cathode electrode, the parasitic PNP bipolar transistor turns on to flow a large discharge current.

Abstract: An ESD protection element is formed by a PN junction diode including an N+ type buried layer having a proper impurity concentration and a first P+ type buried layer and a parasitic PNP bipolar transistor which uses a second P+ type buried layer connected to a P+ type diffusion layer as the emitter, an N? type epitaxial layer as the base, and the first P+ type buried layer as the collector. The first P+ type buried layer is connected to an anode electrode, and the P+ type diffusion layer and an N+ type diffusion layer surrounding the P+ type diffusion layer are connected to a cathode electrode. When a large positive static electricity is applied to the cathode electrode, and the parasitic PNP bipolar transistor turns on to flow a large discharge current.

Abstract: The invention provides a current detection circuit for a transistor, that does not influence a current flowing through the transistor, and minimizes a power loss, an increase of the pattern area and so on. A current detection circuit includes a wiring connected to a MOS transistor and forming a current path of a current of the MOS transistor, a current detection MOS transistor of which the gate is connected to the wiring, that flows a current corresponding to the potential of the gate, and a current detector detecting a current flowing through the current detection MOS transistor. The current detection circuit is configured including a load resistor connected to the current detection MOS transistor and a voltage detection circuit detecting a drain voltage of the current detection MOS transistor.

Abstract: An ESD protection element is formed by a PN junction diode including an N+ type buried layer having a proper impurity concentration and a P+ type buried layer and a parasitic PNP bipolar transistor which uses a P+ type drawing layer connected to a P+ type diffusion layer as the emitter, an N? type epitaxial layer as the base, and a P type semiconductor substrate as the collector. The P+ type buried layer is connected to an anode electrode, and the P+ type diffusion layer and an N+ type diffusion layer connected to and surrounding the P+ type diffusion layer are connected to a cathode electrode. When a large positive static electricity is applied to the cathode electrode, the parasitic PNP bipolar transistor turns on to flow a large discharge current.

Abstract: An ESD protection element is formed by a PN junction diode including an N+ type buried layer having a proper impurity concentration and a first P+ type buried layer and a parasitic PNP bipolar transistor which uses a second P+ type buried layer connected to a P+ type diffusion layer as the emitter, an N? type epitaxial layer as the base, and the first P+ type buried layer as the collector. The first P+ type buried layer is connected to an anode electrode, and the P+ type diffusion layer and an N+ type diffusion layer surrounding the P+ type diffusion layer are connected to a cathode electrode. When a large positive static electricity is applied to the cathode electrode, and the parasitic PNP bipolar transistor turns on to flow a large discharge current.

Abstract: A PN junction diode is formed by an N+ type buried layer having a proper impurity concentration and a P+ type buried layer. The P+ type buried layer is combined with a P+ type drawing layer to penetrate an N? type epitaxial layer and be connected to an anode electrode. An N+ type diffusion layer and a P+ type diffusion layer connected to and surrounding the N+ type diffusion layer are formed in the N? type epitaxial layer surrounded by the P+ type buried layer etc. The N+ type diffusion layer and the P+ type diffusion layer are connected to a cathode electrode. An ESD protection element is formed by the PN junction diode and a parasitic PNP bipolar transistor which uses the P+ type diffusion layer as the emitter, the N? type epitaxial layer as the base, and the P+ type drawing layer etc as the collector.

Abstract: The invention provides a DMOS transistor in which a leakage current is decreased and the source-drain breakdown voltage of the transistor in the off state is enhanced when a body layer is formed by oblique ion implantation. After a photoresist layer 18 is formed, using the photoresist layer 18 and a gate electrode 14 as a mask, first ion implantation is performed toward a first corner portion 14C1 on the inside of the gate electrode 14 in a first direction shown by an arrow A?. A first body layer 17A? is formed by this first ion implantation. The first body layer 17A? is formed so as to extend from the first corner portion 14C1 to under the gate electrode 14, and the P-type impurity concentration of the body layer 17A? in the first corner portion 14C1 is higher than that of a conventional transistor.

Abstract: The invention is directed to a semiconductor device which is manufactured by a BiCMOS process in which a process of manufacturing a V-NPN transistor is rationalized. Furthermore, the hFE of the transistor is adjusted to a large value. An N type base width control layer is formed being in contact with a bottom portion of a P type base region under an N+ type emitter region. The N type base width control layer shallows a portion of the P type base region under the N+ type emitter region partially. The P type base region is formed by using a process of forming a P type well region, and the N type base width control layer is formed by using a process of forming an N type well region, thereby achieving the process rationalization.

Abstract: In the semiconductor device according to the present invention, a P type diffusion layer and an N type diffusion layer as a drain lead region are formed on an N type diffusion layer as a drain region. The P type diffusion layer is disposed between a source region and the drain region of the MOS transistor. When a positive ESD surge is applied to a drain electrode, causing an on-current of a parasite transistor to flow, this structure allows the on-current of the parasite transistor to take a path flowing through a deep portion of an epitaxial layer. Thus, the heat breakdown of the MOS transistor is prevented.

Abstract: A conventional semiconductor device has a problem that an on-current of a parasitic transistor flows through a surface portion of a semiconductor layer and thus a semiconductor element undergoes thermal breakdown. In a semiconductor device according to the present invention, a protection element is formed with use of an isolation region and N type buried layers. A PN junction region in the protection element is formed on a P type buried layer of the isolation region. The PN junction region has a junction breakdown voltage lower than that of a PN junction region of a semiconductor element to be protected. This structure allows an on-current of a parasitic transistor to flow into the protection element, and thereby the semiconductor element is protected. In addition, the on-current of the parasitic transistor flows through a deep portion of the epitaxial layer, and thereby the protection element is prevented from thermal breakdown.

Abstract: An N type layer made of an N type epitaxial layer in which an N+ type drain layer etc are formed is surrounded by a P type drain isolation layer extending from the front surface of the N type epitaxial layer to an N+ type buried layer. A P type collector layer is formed in an N type layer made of the N type epitaxial layer surrounded by the P type drain isolation layer and a P type element isolation layer, extending from the front surface to the inside of the N type layer. A parasitic bipolar transistor that uses the first conductive type drain isolation layer as the emitter, the second conductive type N type layer as the base, and the collector layer as the collector is thus formed so as to flow a surge current into a ground line.

Abstract: A method of fabricating a semiconductor device includes a first step of forming a defect suppression film suppressing increase in a defect due to implantation of an impurity on a semiconductor substrate, a second step of forming an active region on a surface of the semiconductor substrate by implanting the impurity through the defect suppression film, a third step of removing the defect suppression film and a fourth step of forming an interface state suppression film suppressing increase in an interface state density of the active region on the active region.

Abstract: An ON resistance of a trench gate type transistor and a withstand voltage of a planar type transistor are optimized at the same time. Each of first and second regions of a semiconductor layer is formed by epitaxial growth on each of first and second regions of a semiconductor substrate, respectively. A first buried layer is formed between the first region of the semiconductor substrate and the first region of the semiconductor layer, while a second buried layer is formed between the second region of the semiconductor substrate and the second region of the semiconductor layer. The first buried layer is formed of an N+ type first impurity-doped layer and an N type second impurity-doped layer that extends beyond the fist impurity-doped layer. The second buried layer is formed of an N+ type impurity-doped layer only. In the first region of the semiconductor layer, an impurity is diffused from a surface of the semiconductor layer deep into the semiconductor layer to form an N type third impurity-doped layer.

Abstract: A breakdown voltage of a clamp diode can be reduced while a leakage current is suppressed. A P? type diffusion layer is formed in a surface of an N? type semiconductor layer. An N+ type diffusion layer is formed in a surface of the P? type diffusion layer. A P+ type diffusion layer is formed adjacent the N+ type diffusion layer in the surface of the P? type diffusion layer. An N+ type diffusion layer is formed adjacent the P? type diffusion layer in the surface of the N? type semiconductor layer. There is formed a cathode electrode, which is electrically connected with the N+ type diffusion layer through a contact hole formed in an insulation film on the N+ type diffusion layer. There is formed a wiring (an anode electrode) connecting between the P+ type diffusion layer and the N+ type diffusion layer through a contact hole formed in the insulation film on the P+ type diffusion layer and a contact hole formed in the insulation film on the N+ type diffusion layer.

Abstract: The invention provides a current detection circuit for a transistor, that does not influence a current flowing through the transistor, and minimizes a power loss, an increase of the pattern area and so on. A current detection circuit includes a wiring connected to a MOS transistor and forming a current path of a current of the MOS transistor, a current detection MOS transistor of which the gate is connected to the wiring, that flows a current corresponding to the potential of the gate, and a current detector detecting a current flowing through the current detection MOS transistor. The current detection circuit is configured including a load resistor connected to the current detection MOS transistor and a voltage detection circuit detecting a drain voltage of the current detection MOS transistor.

Abstract: A semiconductor device includes a gate electrode formed through an insulating film in a groove having a first side surface adjacent to a source region and a base region, and a second conductive type first impurity region formed adjacent to a second side surface of the groove between the groove and a lead-out portion of a drain region existing below the base region so as to extend downward beyond a lower end of the groove.

Abstract: In a semiconductor device of the present invention, an N type epitaxial layer is divided into a plurality of element formation regions by an isolation region. In one of the element formation regions, a MOS transistor is formed. Around the MOS transistor, a protection element having a PN junction region is formed. The PN junction region has a junction breakdown voltage lower than that of a PN junction region of the MOS transistor. By use of this structure, when negative ESD surge is applied to a pad for a source electrode, the PN junction region of the protection element breaks down. Accordingly, the MOS transistor can be protected.