Abstract: A hold error correction method for complicated large scale integration in a semiconductor is provided. Based on timing analyses, hold error path start point information including a set of a hold error amount at a start point and a minimum value in set-up margins for all data paths starting from the start point, and hold error path end point information including a set of a hold error amount at an end point and a minimum value in set-up margins for all data paths reaching the end point, in association with a failed hold error path, is obtained. The hold error path is classified based on whether the hold error is correctable according to the obtained information. The correctable hold error path is grouped based on a certain criterion. Finally, which of the start point and the end point a delay buffer is inserted into is determined per group.

Abstract: A failure detection improvement apparatus that modifies a net list comprises; a net list input section to which the net list is input; a circuit modification section that adds an observation FF to an appropriate location on the net list; and a net list output section that outputs the net list that has been modified by the circuit modification section.

Abstract: There is provided a circuit design apparatus that performs logic design for realizing a reduction of power consumption and circuit simplification. A circuit design apparatus interprets RTL of a design target to perform structure analysis thereof (S2), estimates generation of a clock gating based on a result of the structure analysis, detects RTL description of an EN generation logic (S3), and detects the same EN generation logic (S4). The apparatus determines an insertion location of the clock gating circuit and reorganization of logical hierarchies based on the detected EN generation logic (S5), instructs logical hierarchy reorganization to be performed in logic synthesis (S8) and performs design change processing (S6). The apparatus performs logic synthesis based on RTL after design change and instruction of logical hierarchy reorganization (S10), and layouts a concrete circuit configuration (S12).

Abstract: A failure detection improvement apparatus that modifies a net list comprises; a net list input section to which the net list is input; a circuit modification section that adds an observation FF to an appropriate location on the net list; and a net list output section that outputs the net list that has been modified by the circuit modification section.