Patents by Inventor Seiji Suetake
Seiji Suetake has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8606974Abstract: A direct memory access controller is provided, in which an internal storage section storing control setting information; and a control section loading the control setting information from an external storage section to the internal storage section when a transfer request signal does not belong to a first group, and not loading the control setting information from the external storage section to the internal storage section when the transfer request signal belongs to the first group; are included, and a data transfer by a direct memory access is performed in accordance with the control setting information within the internal storage section.Type: GrantFiled: March 24, 2010Date of Patent: December 10, 2013Assignee: Fujitsu Semiconductor LimitedInventors: Koji Takenouchi, Seiji Suetake
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Publication number: 20100180053Abstract: A direct memory access controller is provided, in which an internal storage section storing control setting information; and a control section loading the control setting information from an external storage section to the internal storage section when a transfer request signal does not belong to a first group, and not loading the control setting information from the external storage section to the internal storage section when the transfer request signal belongs to the first group; are included, and a data transfer by a direct memory access is performed in accordance with the control setting information within the internal storage section.Type: ApplicationFiled: March 24, 2010Publication date: July 15, 2010Applicant: Fujitsu Microelectronics LimitedInventors: Koji Takenouchi, Seiji Suetake
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Patent number: 7716390Abstract: A direct memory access controller is provided, in which an internal storage section storing control setting information; and a control section loading the control setting information from an external storage section to the internal storage section when a transfer request signal does not belong to a first group, and not loading the control setting information from the external storage section to the internal storage section when the transfer request signal belongs to the first group; are included, and a data transfer by a direct memory access is performed in accordance with the control setting information within the internal storage section.Type: GrantFiled: February 20, 2007Date of Patent: May 11, 2010Assignee: Fujitsu Microelectronics LimitedInventors: Koji Takenouchi, Seiji Suetake
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Patent number: 7634593Abstract: A system for DMA transfer includes a DMA controller, a bus connected to the DMA controller, a bus interface connected to the bus, and a plurality of registers coupled to the bus via the bus interface, wherein the bus interface is configured to allocate the plurality of registers doubly to nonconsecutive addresses and consecutive addresses to allow the DMA controller to access the plurality of registers through the consecutive addresses.Type: GrantFiled: June 24, 2005Date of Patent: December 15, 2009Assignee: Fujitsu Microelectronics LimitedInventor: Seiji Suetake
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Patent number: 7434079Abstract: A microcomputer that can increase the usage efficiency of a cache memory and increase the process speed is provided. In this microcomputer, a group of registers hold cache usage information that specifies whether the cache memory is to be used in execution of a process. When processes to be executed are switched, a process switch control circuit obtains the cache usage information of the next process from the group of registers, and stores the cache usage information in a first register. After the storing of the cache usage information in the first register, a cache control circuit stores the cache usage information in a second register. In accordance with the cache usage information stored in the second register, the cache control circuit puts the cache memory in a usable state or an unusable state.Type: GrantFiled: December 13, 2005Date of Patent: October 7, 2008Assignee: Fujitsu LimitedInventor: Seiji Suetake
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Publication number: 20080040517Abstract: A direct memory access controller is provided, in which an internal storage section storing control setting information; and a control section loading the control setting information from an external storage section to the internal storage section when a transfer request signal does not belong to a first group, and not loading the control setting information from the external storage section to the internal storage section when the transfer request signal belongs to the first group; are included, and a data transfer by a direct memory access is performed in accordance with the control setting information within the internal storage section.Type: ApplicationFiled: February 20, 2007Publication date: February 14, 2008Applicant: FUJITSU LIMITEDInventors: Koji Takenouchi, Seiji Suetake
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Patent number: 7162563Abstract: A data controlling unit activates a predetermined number of data terminals according to a mode signal and changes a bus width of external data signal. According to the mode signal, an address controlling unit selects a predetermined number of bits of an internal address signal outputted from a controller and outputs the selected bits as an external address signal. Specifically, the address controlling unit selects upper bits of the internal address signal when the bus width of the external data signal is increased according to the mode signal. Therefore, it is possible to prevent occurrence of an unused external address terminal, enabling the increase in accessible external memory capacity.Type: GrantFiled: July 26, 2004Date of Patent: January 9, 2007Assignee: Fujitsu LimitedInventors: Satoshi Matsui, Seiji Suetake
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Publication number: 20060206633Abstract: A system for DMA transfer includes a DMA controller, a bus connected to the DMA controller, a bus interface connected to the bus, and a plurality of registers coupled to the bus via the bus interface, wherein the bus interface is configured to allocate the plurality of registers doubly to nonconsecutive addresses and consecutive addresses to allow the DMA controller to access the plurality of registers through the consecutive addresses.Type: ApplicationFiled: June 24, 2005Publication date: September 14, 2006Applicant: FUJITSU LIMITEDInventor: Seiji Suetake
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Publication number: 20060095810Abstract: A microcomputer that can increase the usage efficiency of a cache memory and increase the process speed is provided. In this microcomputer, a group of registers hold cache usage information that specifies whether the cache memory is to be used in execution of a process. When processes to be executed are switched, a process switch control circuit obtains the cache usage information of the next process from the group of registers, and stores the cache usage information in a first register. After the storing of the cache usage information in the first register, a cache control circuit stores the cache usage information in a second register. In accordance with the cache usage information stored in the second register, the cache control circuit puts the cache memory in a usable state or an unusable state.Type: ApplicationFiled: December 13, 2005Publication date: May 4, 2006Applicant: FUJITSU LIMITEDInventor: Seiji Suetake
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Patent number: 7012454Abstract: A circuit for changing clocks includes a clock generating circuit which generates an output clock signal by controlling a frequency of an original clock signal, and a control circuit which controls the clock generating circuit in response to an operation mode change signal indicative of a change from a first operation mode to a second operation mode of an external circuit operating based on the output clock signal, thereby changing the output clock signal from a first frequency corresponding to the first operation mode to an intervening frequency and then from the intervening frequency to a second frequency corresponding to the second operation mode, the intervening frequency having a frequency between the first frequency and the third frequency.Type: GrantFiled: March 10, 2004Date of Patent: March 14, 2006Assignee: Fujitsu LimitedInventors: Satoshi Matsui, Yukihiro Ozawa, Seiji Suetake
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Patent number: 7007134Abstract: A microcomputer that can increase the usage efficiency of a cache memory and increase the process speed is provided. In this microcomputer, a group of registers hold cache usage information that specifies whether the cache memory is to be used in execution of a process. When processes to be executed are switched, a process switch control circuit obtains the cache usage information of the next process from the group of registers, and stores the cache usage information in a first register. After the storing of the cache usage information in the first register, a cache control circuit stores the cache usage information in a second register. In accordance with the cache usage information stored in the second register, the cache control circuit puts the cache memory in a usable state or an unusable state.Type: GrantFiled: January 31, 2003Date of Patent: February 28, 2006Assignee: Fujitsu LimitedInventor: Seiji Suetake
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Publication number: 20050182885Abstract: A data controlling unit activates a predetermined number of data terminals according to a mode signal and changes a bus width of external data signal. According to the mode signal, an address controlling unit selects a predetermined number of bits of an internal address signal outputted from a controller and outputs the selected bits as an external address signal. Specifically, the address controlling unit selects upper bits of the internal address signal when the bus width of the external data signal is increased according to the mode signal. Therefore, it is possible to prevent occurrence of an unused external address terminal, enabling the increase in accessible external memory capacity.Type: ApplicationFiled: July 26, 2004Publication date: August 18, 2005Applicant: Fujitsu LimitedInventors: Satoshi Matsui, Seiji Suetake
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Publication number: 20050083098Abstract: A circuit for changing clocks includes a clock generating circuit which generates an output clock signal by controlling a frequency of an original clock signal, and a control circuit which controls the clock generating circuit in response to an operation mode change signal indicative of a change from a first operation mode to a second operation mode of an external circuit operating based on the output clock signal, thereby changing the output clock signal from a first frequency corresponding to the first operation mode to an intervening frequency and then from the intervening frequency to a second frequency corresponding to the second operation mode, the intervening frequency having a frequency between the first frequency and the third frequency.Type: ApplicationFiled: March 10, 2004Publication date: April 21, 2005Applicant: FUJITSU LIMITEDInventors: Satoshi Matsui, Yukihiro Ozawa, Seiji Suetake
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Patent number: 6880066Abstract: A central processing system can maintain an efficient information reading operation even when a program executed by a central processing unit contains many branch commands. A prefetch queue of the central processing unit reads and information expected to be processed next by the central processing unit from a main memory. The function of the prefetch queue is deactivated in accordance with a control signal provided from a prefetch queue control unit. A block transfer function of a cache memory is also deactivated when unnecessary information is read from the main memory in accordance with the block transfer function.Type: GrantFiled: October 20, 1999Date of Patent: April 12, 2005Assignee: Fujitsu LimitedInventor: Seiji Suetake
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Publication number: 20040172518Abstract: Provided is an information processing unit including: a prefetch buffer for fetching an instruction through a bus with its width being twice or more as large as an instruction length, to store the prefetched instruction; a decoder for decoding the instruction stored in the prefetch buffer; and an arithmetic unit for executing the decoded instruction. An instruction request control circuit performs a prefetch request to prefetch a branch target instruction when a branch instruction is decoded, otherwise the instruction request control circuit performs the prefetch request sequentially to prefetch the instructions. A prefetch control circuit fetches the branch target instruction to the prefetch buffer when the branch is ensured to occur by executing the branch instruction, while the prefetch control circuit ignores the branch target instruction when a branch does not occur.Type: ApplicationFiled: October 17, 2003Publication date: September 2, 2004Applicant: FUJITSU LIMITEDInventors: Toshiaki Saruwatari, Seiji Suetake
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Patent number: 6708266Abstract: The central processing unit is provided with an instruction queue storage section. This central processing unit is made of a memory, such as FIFO memory, that adopts first-in first-out method. A counter counters each time an instruction datum is stored in the instruction queue storage section. When the value of the counter is 0 or 1 and instruction fetch is not suppressed, a fetch request is issued.Type: GrantFiled: January 25, 2001Date of Patent: March 16, 2004Assignee: Fujitsu LimitedInventor: Seiji Suetake
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Publication number: 20030167378Abstract: A microcomputer that can increase the usage efficiency of a cache memory and increase the process speed is provided. In this microcomputer, a group of registers hold cache usage information that specifies whether the cache memory is to be used in execution of a process. When processes to be executed are switched, a process switch control circuit obtains the cache usage information of the next process from the group of registers, and stores the cache usage information in a first register. After the storing of the cache usage information in the first register, a cache control circuit stores the cache usage information in a second register. In accordance with the cache usage information stored in the second register, the cache control circuit puts the cache memory in a usable state or an unusable state.Type: ApplicationFiled: January 31, 2003Publication date: September 4, 2003Applicant: Fujitsu LimitedInventor: Seiji Suetake
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Publication number: 20030110365Abstract: A central processing system can maintain an efficient information reading operation even when a program executed by a central processing unit contains many branch commands. A prefetch queue of the central processing unit reads and information expected to be processed next by the central processing unit from a main memory. The function of the prefetch queue is deactivated in accordance with a control signal provided from a prefetch queue control unit. A block transfer function of a cache memory is also deactivated when unnecessary information is read from the main memory in accordance with the block transfer function.Type: ApplicationFiled: October 20, 1999Publication date: June 12, 2003Inventor: SEIJI SUETAKE
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Patent number: 6535960Abstract: An information processing device includes a central processing unit, a cache memory unit and first and second decision circuits. The first decision circuit identifies one of partitioned address areas to be accessed before the central processing unit accesses the cache memory unit. The second decision circuit determines whether the above one of the partitioned address areas is a cachable area or a non-cachable area before address tag data is referred to in the cache memory unit.Type: GrantFiled: May 8, 1998Date of Patent: March 18, 2003Assignee: Fujitsu LimitedInventors: Syuji Nishida, Seiji Suetake, Shunsuke Kamijo, Kenji Furuya
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Publication number: 20010011340Abstract: The central processing unit is provided with an instruction queue storage section. This central processing unit is made of a memory, such as FIFO memory, that adopts first-in first-out method. A counter counters each time an instruction datum is stored in the instruction queue storage section. When the value of the counter is 0 or 1 and instruction fetch is not suppressed, a fetch request is issued.Type: ApplicationFiled: January 25, 2001Publication date: August 2, 2001Inventor: Seiji Suetake