Abstract: A non-volatile memory device (100) comprises a memory cell (11A, 11B) that is, in an initial state, in a state of having storage data of a first logical value stored therein, and that is, after execution of a program operation, in a state of having storage data of a second logical value stored therein, and an error correction circuit (14) that corrects only an error caused by a change in logical value of the storage data stored in the memory cell from the second logical value to the first logical value.

Abstract: There are disposed second and third transistors whose gates are connected to each other, and first and fourth transistors whose gates are connected to each other. Sources of the first to fourth transistors are connected to each other. A read operation is performed in a state where drain current is supplied to the fourth transistor, and drain current larger than that of the fourth transistor is supplied to the third transistor. In the read operation, a signal associated with a first or second value is output based on drain currents of the first and second transistors.

Abstract: A non-volatile memory includes a memory cell having a first transistor and a second transistor, a driving circuit arranged to apply a read voltage to gates of the first and second transistors, and a signal output circuit arranged to output a signal associated with a first value or a signal associated with a second value, based on drain currents of the first and second transistors, in a read operation in which the read voltage is applied. The second transistor is constituted of a parallel circuit of a plurality of unit transistors, and gate width of each of the unit transistors is larger than that of the first transistor.

Abstract: A memory cell has a first transistor and a second transistor. A drive circuit includes a boost circuit configured to generate a boost voltage on a boost line by boosting a predetermined reference voltage, and an adjustment circuit configured to adjust the boost voltage by drawing from the boost line an adjustment current commensurate with the boost voltage. The drive circuit feeds the adjusted boost voltage as the read voltage to the gates of the first and second transistors. In a read operation in which the read voltage is fed, the signal output circuit outputs a signal associated with a first value or a signal associated with a second value based on the drain currents in the first and second transistors.

Abstract: A non-volatile memory has: a first and a second transistor having their gates connected together; a resistor having a first and a second terminal, with the first terminal connected to the source of the first transistor; a read voltage feed circuit configured to feed a read voltage for turning on at least one of the first and second transistors to between the gate of the first transistor and the second terminal of the resistor and to between the gate and the source of the second transistor; and a signal output circuit configured to output, in a read operation in which the read voltage feed circuit feeds the read voltage, a signal associated with a first or second value based on the drain currents of the first and second transistors.

Abstract: This switching power source 100 has: a switching output circuit 110 which drives an inductor current IL by turning on and off an upper switch 111 and a lower switch 112 and generates an output voltage VOUT from an input voltage PVDD; a lower current detection unit 210 which detects the inductor current IL flowing through the lower switch 112 during an ON-period of the lower switch 112 and acquires lower current feedback information Iinfo; an error amplifier 140 which outputs voltage feedback information Vinfo including information on an error between the output voltage VOUT (feedback voltage FB) and a reference voltage REF; an information synthesis unit 220 that generates synthesis feedback information VIinfo by synthesizing Iinfo with Vinfo; and an information holding unit 230 which samples Vinfo during the ON-period of the lower switch 112.

Abstract: This switching power source 100 has: a switching output circuit 110 which drives an inductor current IL by turning on and off an upper switch 111 and a lower switch 112 and generates an output voltage VOUT from an input voltage PVDD; a lower current detection unit 210 which detects the inductor current IL flowing through the lower switch 112 during an ON-period of the lower switch 112 and acquires lower current feedback information Iinfo; an error amplifier 140 which outputs voltage feedback information Vinfo including information on an error between the output voltage VOUT (feedback voltage FB) and a reference voltage REF; an information synthesis unit 220 that generates synthesis feedback information VIinfo by synthesizing Iinfo with Vinfo; and an information holding unit 230 which samples Vinfo during the ON-period of the lower switch 112.

Abstract: This switching power source 100 has: a switching output circuit 110 which drives an inductor current IL by turning on and off an upper switch 111 and a lower switch 112 and generates an output voltage VOUT from an input voltage PVDD; a lower current detection unit 210 which detects the inductor current IL flowing through the lower switch 112 during an ON-period of the lower switch 112 and acquires lower current feedback information Iinfo; an error amplifier 140 which outputs voltage feedback information Vinfo including information on an error between the output voltage VOUT (feedback voltage FB) and a reference voltage REF; an information synthesis unit 220 that generates synthesis feedback information VIinfo by synthesizing Iinfo with Vinfo; and an information holding unit 230 which samples Vinfo during the ON-period of the lower switch 112.

Abstract: This switching power source 100 has: a switching output circuit 110 which drives an inductor current IL by turning on and off an upper switch 111 and a lower switch 112 and generates an output voltage VOUT from an input voltage PVDD; a lower current detection unit 210 which detects the inductor current IL flowing through the lower switch 112 during an ON-period of the lower switch 112 and acquires lower current feedback information Iinfo; an error amplifier 140 which outputs voltage feedback information Vinfo including information on an error between the output voltage VOUT (feedback voltage FB) and a reference voltage REF; an information synthesis unit 220 that generates synthesis feedback information VIinfo by synthesizing Iinfo with Vinfo; and an information holding unit 230 which samples Vinfo during the ON-period of the lower switch 112.

Abstract: An OTP readout circuit includes an OTP circuit having a first OTP cell in which data is programmable only once, and a readout-possible signal output unit configured to generate a readout-possible voltage for reading out the data and output the generated readout-possible voltage to the OTP circuit. The readout-possible voltage from the readout-possible signal output unit causes the OTP circuit to read out the data programmed into the first OTP cell.

Abstract: This switching power source 100 has: a switching output circuit 110 which drives an inductor current IL by turning on and off an upper switch 111 and a lower switch 112 and generates an output voltage VOUT from an input voltage PVDD; a lower current detection unit 210 which detects the inductor current IL flowing through the lower switch 112 during an ON-period of the lower switch 112 and acquires lower current feedback information Iinfo; an error amplifier 140 which outputs voltage feedback information Vinfo including information on an error between the output voltage VOUT (feedback voltage FB) and a reference voltage REF; an information synthesis unit 220 that generates synthesis feedback information VIinfo by synthesizing Iinfo with Vinfo; and an information holding unit 230 which samples Vinfo during the ON-period of the lower switch 112.

Abstract: A switching power supply includes: a switching output circuit configured to generate an output voltage from an input voltage by charging a capacitor by turning on and off an output transistor; a control circuit configured to halt the driving of the switching output circuit when charging electric charge to the capacitor per switching event is limited to a lower limit value and the output voltage, or a feedback voltage commensurate therewith, is raised from a predetermined reference voltage; and a lower limit value setting circuit configured to variably control the lower limit value during the driven period of the switching output circuit. For example, the lower limit value setting circuit can increase the lower limit value with increase in the number of times of switching.

Abstract: A switching power supply circuit includes a switching output unit that generates an output voltage from an input voltage using an output transistor, a switching control unit that controls on and off of the output transistor so that the output voltage or a feedback voltage in proportion to the output voltage agrees with a predetermined reference voltage, and one of an interrupt unit and a reference voltage setting unit. The interrupt unit forcibly turns off the output transistor during a period while the output voltage or the feedback voltage is higher than a threshold value voltage that is higher than the reference voltage in response to a periodic load change. The reference voltage setting unit temporarily changes the reference voltage in synchronization with timing of a periodic load change.

Abstract: A switching power supply includes: a switching output circuit configured to generate an output voltage from an input voltage by charging a capacitor by turning on and off an output transistor; a control circuit configured to halt the driving of the switching output circuit when charging electric charge to the capacitor per switching event is limited to a lower limit value and the output voltage, or a feedback voltage commensurate therewith, is raised from a predetermined reference voltage; and a lower limit value setting circuit configured to variably control the lower limit value during the driven period of the switching output circuit. For example, the lower limit value setting circuit can increase the lower limit value with increase in the number of times of switching.

Abstract: A switching power supply circuit has a switching output stage which generates an output voltage from an input voltage by driving a coil current by using an output transistor and a switching controller which turns ON and OFF the output transistor to keep the output voltage or a feedback voltage commensurate with it equal to a predetermined reference voltage. The switching controller includes a reference slope voltage generator which generates a reference slope voltage, a sense voltage holder which generates a held sense voltage by latching a sense voltage commensurate with the coil current with predetermined timing, and a voltage adder which generates a slope voltage by adding up the reference slope voltage and the held sense voltage. The switching controller determines the ON duty of the output transistor by using the slope voltage.

Abstract: An oscillation circuit includes: a periodic signal generator which generates a periodic signal whose frequency varies; and a clock generator which generates a clock signal having a frequency commensurate with the frequency of the periodic signal.

Abstract: A switching power supply circuit has: a switching output generator that generates an output voltage from an input voltage by using an output transistor; a switching controller that turns ON and OFF the output transistor so as to keep the output voltage, or a feedback voltage commensurate therewith, with a predetermined reference voltage; and a maximum duty controller that varies the maximum duty of the output transistor according to the reference voltage, the output voltage, or the feedback voltage.

Abstract: An error amplifier amplifies a difference between a feedback signal VFB that corresponds to an output voltage VOUT of a DC/DC converter and its target value VREF, so as to generate an error signal VERR. A pulse width modulator for each channel is configured as a peak current mode modulator comprising a PWM comparator that compares a current detection signal VIS with the error signal VERR, and a logic circuit. When the number of enabled channels is switched, a soft shedding circuit selects at least one channel as a correction target channel. The soft shedding circuit generates a correction signal VCORR for each correction target channel, and superimposes each correction signal VCORR on at least one of two inputs of the corresponding PWM comparator.

Abstract: An oscillation circuit includes: a periodic signal generator which generates a periodic signal whose frequency varies; and a clock generator which generates a clock signal having a frequency commensurate with the frequency of the periodic signal.

Abstract: An error amplifier amplifies a difference between a feedback signal VFB that corresponds to an output voltage VOUT of a DC/DC converter and its target value VREF, so as to generate an error signal VERR. A pulse width modulator for each channel is configured as a peak current mode modulator comprising a PWM comparator that compares a current detection signal VIS with the error signal VERR, and a logic circuit. When the number of enabled channels is switched, a soft shedding circuit selects at least one channel as a correction target channel. The soft shedding circuit generates a correction signal VCORR for each correction target channel, and superimposes each correction signal VCORR on at least one of two inputs of the corresponding PWM comparator.