Abstract: A first receiver receives serial data including multiple odd-numbered pixels arranged horizontally at odd-numbered positions in a frame. A second receiver receives serial data including multiple even-numbered pixels arranged horizontally at even-numbered positions in a frame. A signal processing unit integrates the multiple odd-numbered and even-numbered pixels, so as to generate line data. A first reception abnormal state detector detects an abnormal state in the first receiver. A second reception abnormal state detector detects an abnormal state in the second receiver. When the first reception abnormal state detector detects an abnormal state, the signal processing unit restores odd-numbered pixels using even-numbered pixels. When the second reception abnormal state detector detects an abnormal state, the signal processing unit restores even-numbered pixels using odd-numbered pixels.

Abstract: A first receiver receives serial data including multiple odd-numbered pixels arranged horizontally at odd-numbered positions in a frame. A second receiver receives serial data including multiple even-numbered pixels arranged horizontally at even-numbered positions in a frame. A signal processing unit integrates the multiple odd-numbered and even-numbered pixels, so as to generate line data. A first reception abnormal state detector detects an abnormal state in the first receiver. A second reception abnormal state detector detects an abnormal state in the second receiver. When the first reception abnormal state detector detects an abnormal state, the signal processing unit restores odd-numbered pixels using even-numbered pixels. When the second reception abnormal state detector detects an abnormal state, the signal processing unit restores even-numbered pixels using odd-numbered pixels.

Abstract: A reception interface circuit receives a luminance signal for each of multiple colors and a clock signal as input signals. A timing control unit receives the luminance signals received by the reception interface circuit, and controls the timing and format thereof such that they match drivers. A transmission interface circuit transmits the signals generated by the timing controller IC to the drivers. The timing controller IC is included within a rectangular package as a built-in component. The reception interface circuit is arranged on a first short side of the package. The transmission interface circuit is arranged on a second short side of the package. The image data is input via input terminals arranged on the first short side. The output signals of the transmission interface circuit are output via output terminals arranged on the second short side.

Abstract: A clock distribution circuit receives a clock signal, and distributes the clock signal thus received to multiple paths. A digital circuit is configured as multiple separate regions, each associated with a respective one of the multiple paths. Each region receives a common power supply voltage Vdd. Furthermore, each region operates synchronously with the corresponding clock signal thus distributed by the clock distribution circuit. When the clock signal transmits from the non-input state to the input state, the clock distribution circuit each distributes the clock signal to the multiple paths in a temporally staggered manner.

Abstract: A reception interface circuit receives a luminance signal for each of multiple colors and a clock signal as input signals. A timing control unit receives the luminance signals received by the reception interface circuit, and controls the timing and format thereof such that they match drivers. A transmission interface circuit transmits the signals generated by the timing controller IC to the drivers. The timing controller IC is included within a rectangular package as a built-in component. The reception interface circuit is arranged on a first short side of the package. The transmission interface circuit is arranged on a second short side of the package. The image data is input via input terminals arranged on the first short side. The output signals of the transmission interface circuit are output via output terminals arranged on the second short side.