Patents by Inventor Seiji Ueda

Seiji Ueda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8389125
    Abstract: Provided are a formaldehyde scavenger capable of providing excellent formaldehyde scavenging performance without discoloring a wood material and not reemitting formaldehyde, and a wood material using the same. The formaldehyde scavenger contains urea, ammonium phosphate monobasic and ammonium phosphate dibasic. The formaldehyde scavenger contains urea, ammonium phosphate monobasic and ammonium phosphate dibasic preferably in a weight ratio of urea/ammonium phosphate monobasic/ammonium phosphate dibasic in the range of 5 to 45/0.5 to 15/1 to 20, and further preferably in a weight ratio of urea/ammonium phosphate monobasic/ammonium phosphate dibasic in the range of 10 to 35/1 to 10/2 to 15. The wood material is prepared by applying the formaldehyde scavenger thereto. The formaldehyde scavenger is preferably applied in the range of 1 to 50 g/m2 by dry weight.
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: March 5, 2013
    Assignee: Idemitsu Technofine Co., Ltd.
    Inventors: Ichiro Fujii, Yuji Murata, Seiji Ueda, Shigeo Negishi, Toshiharu Taguchi
  • Publication number: 20110171482
    Abstract: Provided are a formaldehyde scavenger capable of providing excellent formaldehyde scavenging performance without discoloring a wood material and not reemitting formaldehyde, and a wood material using the same. The formaldehyde scavenger contains urea, ammonium phosphate monobasic and ammonium phosphate dibasic. The formaldehyde scavenger contains urea, ammonium phosphate monobasic and ammonium phosphate dibasic preferably in a weight ratio of urea/ammonium phosphate monobasic/ammonium phosphate dibasic in the range of 5 to 45/0.5 to 15/1 to 20, and further preferably in a weight ratio of urea/ammonium phosphate monobasic/ammonium phosphate dibasic in the range of 10 to 35/1 to 10/2 to 15. The wood material is prepared by applying the formaldehyde scavenger thereto. The formaldehyde scavenger is preferably applied in the range of 1 to 50 g/m2 by dry weight.
    Type: Application
    Filed: June 26, 2009
    Publication date: July 14, 2011
    Inventors: Ichiro Fujii, Yuji Murata, Seiji Ueda, Shigeo Negishi, Toshiharu Taguchi
  • Patent number: 7800181
    Abstract: A gate electrode is formed on a semiconductor substrate containing silicon, then source/drain regions are formed in regions of the semiconductor substrate located to both sides of the gate electrode, and then a nickel alloy silicide layer is formed on at least either the gate electrode or the source/drain regions. In the step of forming the nickel alloy silicide layer, a nickel alloy film and a nickel film are sequentially deposited on the semiconductor substrate and thereafter subjected to heat treatment.
    Type: Grant
    Filed: October 18, 2006
    Date of Patent: September 21, 2010
    Assignee: Panasonic Corporation
    Inventors: Yasutoshi Okuno, Michikazu Matsumoto, Masafumi Kubota, Seiji Ueda, Hiroshi Iwai, Kazuo Tsutsui, Kuniyuki Kakushima
  • Publication number: 20080105935
    Abstract: A micromachine device includes a pad 107a and a pad 107b formed of a polysilicon doped with impurities.
    Type: Application
    Filed: August 15, 2005
    Publication date: May 8, 2008
    Inventors: Hiroshi Ogura, Seiji Ueda, Katsuhiro Makihata
  • Publication number: 20070093047
    Abstract: A gate electrode is formed on a semiconductor substrate containing silicon, then source/drain regions are formed in regions of the semiconductor substrate located to both sides of the gate electrode, and then a nickel alloy silicide layer is formed on at least either the gate electrode or the source/drain regions. In the step of forming the nickel alloy silicide layer, a nickel alloy film and a nickel film are sequentially deposited on the semiconductor substrate and thereafter subjected to heat treatment.
    Type: Application
    Filed: October 18, 2006
    Publication date: April 26, 2007
    Inventors: Yasutoshi Okuno, Michikazu Matsumoto, Masafumi Kubota, Seiji Ueda, Hiroshi Iwai, Kazuo Tsutsui, Kuniyuki Kakushima
  • Patent number: 6224169
    Abstract: A brake fluid pressure control apparatus for vehicles comprises an electric motor mounted on one side of a housing, an electronic control box mounted on the other side of the housing, and conductive members extending from the electronic control box. The conductive members are inserted in through holes of the housing, and have motor connection male terminals at tip ends thereof. Motor connection male terminals are accommodated in motor accommodation portions provided in the electric motor. The motor connection female terminals and the motor connection male terminals are engaged for electrical connection.
    Type: Grant
    Filed: December 3, 1998
    Date of Patent: May 1, 2001
    Assignee: Sumitomo Electric Industries Ltd.
    Inventors: Katsunori Aoki, Teruhisa Kohno, Seiji Ueda
  • Patent number: 5695259
    Abstract: This invention aims to enhance a production efficiency of an automobile provided with an antilock brake system. A united assembly of an electronic unit 6 and a junction block 7 is detachably mounted on a side face of a hydraulic power unit 5 which controls a pressure of brake fluid. The junction block 7 is provided with a set of terminals 74A connected to solenoids and the like of the hydraulic power unit 5, a set of terminals 74B connected directly or indirectly to a battery 21, a set of terminals 74C and 74D connected to relays 9 and 10, and a set of terminals 74E connected to a circuit of the electronic unit 6. These sets of terminals 74A to 74E are connected through bus bars 74, respectively. It is possible to reduce the number of wire harnesses extending between an engine compartment and a car interior and to realize various kinds of lay-out in the engine compartment.
    Type: Grant
    Filed: December 12, 1995
    Date of Patent: December 9, 1997
    Assignees: Sumitomo Wiring Systems, Ltd.,, Sumitomo Electric Industries, Ltd.
    Inventors: Isao Isshiki, Hitoshi Hashiba, Yoshiharu Nakai, Seiji Ueda, Takao Nozaki, Masahide Hio
  • Patent number: 5685617
    Abstract: There is disclosed a unit integrated system wherein a hydraulic unit (1) having an upper surface (3a) defining an oil inlet and an electronic control unit (2) for controlling the drive of the hydraulic unit (1) are integrated together in juxtaposition with each other in such a manner that an upper surface (2a) of the electronic control unit is located at a position equal to or lower than the upper surface (3a) of the hydraulic unit (1), whereby an operating space (35) of a piping tool is insured above the electronic control unit (2) in connecting a hydraulic pipe (34) to the oil inlet in the upper surface (3a) of the hydraulic unit (1), and the hydraulic pipe (34) is securely connected to the oil inlet of the hydraulic unit (1) by using the existing spanner-shaped piping tool without interference of the tool with an upper portion of the electronic control unit (2).
    Type: Grant
    Filed: May 17, 1996
    Date of Patent: November 11, 1997
    Assignees: Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventors: Masahide Hio, Takao Nozaki, Hitoshi Hashiba, Isao Isshiki, Yoshiharu Nakai, Seiji Ueda, Itaru Wada
  • Patent number: 5533905
    Abstract: A connector having terminal groups (222) intended to carry a large current from a source of electrical power to an actuator for a hydraulic unit. The connector also has another terminal group (223) for a smaller current which is electrically connected to components of an electronic control unit (2) for hydraulic unit (1). Connector housing (221) is provided with base plate (221a) which carries terminal groups (222 and 223) and tubular housing body (221b) encloses both terminal groups (222 and 223). The terminals of both groups are joined at their outer ends to a harness-side connector (219) and at their inner ends the terminal group (222) is joined by wiring (224) to a motor (205) and the terminal group (223) is joined to a printed board (209). The board (209) along with a junction block (210) are housed within a pair of case elements (213a and 213b).
    Type: Grant
    Filed: July 28, 1994
    Date of Patent: July 9, 1996
    Assignees: Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventors: Masahide Hio, Takao Nozaki, Hitoshi Hashiba, Isao Isshiki, Yoshiharu Nakai, Seiji Ueda, Itaru Wada
  • Patent number: 5407260
    Abstract: A hydraulic power unit (5) mounts integrally an electronic unit (6) in an antilock brake system. The unit (5) has a solenoid tab (5ab) containing a coupling pin connected to a coil of a solenoid valve (5a). The electronic unit (6) has a connector for a power source, a motor relay (7), terminal sections (61Ba, 61Bd, and 61Be) for fail-safe relays. The coil in the solenoid valve (5a) is electrically coupled to an electronic control section, and the terminal sections (61Bd and 61Be) in the electronic unit (6) by coupling the solenoid tab 5ba to a solenoid socket (14) in the electronic unit (6). This construction makes it easy to electrically interconnect the coil of the solenoid valve in the hydraulic power unit (5) and the electronic unit (6).
    Type: Grant
    Filed: December 21, 1993
    Date of Patent: April 18, 1995
    Assignees: Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventors: Isao Isshiki, Hitoshi Hashiba, Yoshiharu Nakai, Seiji Ueda, Takao Nozaki, Masahide Hio
  • Patent number: 5084416
    Abstract: The invention is intended to form a recess large in the opening width at the contact hole forming position of the insulator film before opening contact holes in the insulator film, and to open contact holes smaller in opening width at the bottom of the recess.According to the manufacturing method of the invention, since the opening size of the recess in the upper portion of the contact hole may be set larger and by decreasing the shadowing effect when covering the aluminum alloy wiring layer, the degree of covering of the aluminum alloy wiring layer on the side wall of the contact hole is improved, so that reduction of contact resistance and enhancement of reliability may be achieved.
    Type: Grant
    Filed: February 20, 1990
    Date of Patent: January 28, 1992
    Assignee: Matsushita Electronics Corporation
    Inventors: Hideto Ozaki, Shuichi Mayumi, Seiji Ueda
  • Patent number: 4948756
    Abstract: Disclosed is a process for making a semiconductor device which has two polycrystalline layers (5) and (15) isolated by insulation films. Openings are made utilizing a single photoresist mask by etching the polycrystalline silicon layer and the underlying insulation film in one sequence. The polycrystalline silicon layers and diffused regions of the substrate exposed in the openings, are connected with a tungsten film (12) by selective deposition.
    Type: Grant
    Filed: October 28, 1988
    Date of Patent: August 14, 1990
    Assignee: Matsushita Electronics Corporation
    Inventor: Seiji Ueda
  • Patent number: 4797719
    Abstract: A MOS capacitor comprising a semiconductor substrate having a pair of spaced trenches in one surface. An isolation region is located in the substrate between the trenches and first polycrystalline silicon films are formed within each of the trenches directly on the substrate. Insulating films are formed on the first polycrystalline film, and a second polycrystalline film is formed on the insulating films. The first and second polycrystalline films function as first and second electrodes of the MOS capacitor and the insulating film as a dielectric layer of the capacitor.
    Type: Grant
    Filed: March 21, 1988
    Date of Patent: January 10, 1989
    Assignee: Matsushita Electronics Corporation
    Inventor: Seiji Ueda
  • Patent number: 4610076
    Abstract: In a method of manufacturing a semiconductor device, a thin silicon dioxide (SiO.sub.2) film for a gate insulation film and a polycrystalline silicon layer are successively deposited on a semiconductor substrate having one electrical conductivity type whereby this polycrystalline silicon layer has a gate electrode pattern. In this step a part of the polycrystalline silicon layer is left at a part where an electric contact with the substrate is to be formed. Parts of source and drain regions are formed by the self-align method with this polycrystalline silicon layer as a mask. A thick passivation film for an interlayer insulation film is formed to cover the whole surface. An aperture is formed selectively in the passivation film to expose the whole polycrystalline silicon layer at the part where the contact is formed. The polycrystalline silicon layer in the aperture part and the thin insulation film thereunder are removed to expose a part of the semiconductor substrate.
    Type: Grant
    Filed: September 28, 1984
    Date of Patent: September 9, 1986
    Assignee: Matsushita Electronics Corporation
    Inventor: Seiji Ueda
  • Patent number: 4113533
    Abstract: A method of making a MOS device, for instance, metal-oxide semiconductor type integrated circuit, is disclosed which comprises the following steps:Sequentially forming on a specified part of single crystal silicon substrate,Firstly, an oxide film,Secondly, a film to become a conductor film having a high-temperature-resistive nature, which does not melt at an impurity-diffusion temperature, serves as a diffusion mask and later serves as a gate electrode, for instance, polycrystalline silicon film; and thirdly, an oxidation-preventing film for preventing oxidation of said film to become the conductor film, wherein at least said conductor film and said overiding oxidation-preventing film have the same pattern so as to cover and prevent oxidation of said conductor film by said oxidation-preventing film, and thenDiffusing an impurity into the substrate from openings which are the parts other than those covered by said conductor film and said oxidation preventing film,The method being characterized by having a step
    Type: Grant
    Filed: January 28, 1977
    Date of Patent: September 12, 1978
    Assignee: Matsushita Electronics Corporation
    Inventors: Tomisaburo Okumura, Hiroshi Okazaki, Akira Tsuchitani, Seiji Ueda