Patents by Inventor Seiji Yamagata

Seiji Yamagata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100086205
    Abstract: A noise removal circuit in an image signal includes a boundary determination unit configured to determine a position of a light-dark boundary on the basis of, or as a function of, a pixel value of a plurality of surrounding pixels, and a selection filter configured to perform filtering in a range of the plurality of surrounding pixels which belong to a range which does not cross a boundary determined by the boundary determination unit.
    Type: Application
    Filed: February 12, 2009
    Publication date: April 8, 2010
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventor: Seiji YAMAGATA
  • Patent number: 7639290
    Abstract: A differential amplifier has a first input terminal to which a voltage of a noise signal of the solid-state imaging device is supplied and a second input terminal to which a voltage of a temporary data signal having the noise signal of the solid-state imaging device superposed thereon is supplied. The differential amplifier inverts an output signal when a magnitude relationship in voltage between the first and second input terminals becomes reverse. A measurement circuit measures a variation amount of a voltage of the second input terminal from when the voltage of the second input terminal begins to vary in a direction to reverse the magnitude relationship to when the output signal of the differential amplifier is inverted, and outputs a measurement result as a digital value indicating a voltage of a real data signal obtained by removing the noise signal from the temporary data signal.
    Type: Grant
    Filed: May 27, 2005
    Date of Patent: December 29, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Tsuyoshi Higuchi, Jun Funakoshi, Seiji Yamagata, Toshitaka Mizuguchi, Katsuyoshi Yamamoto
  • Patent number: 7477299
    Abstract: A second source follower circuit of a reference voltage generator includes a transistor having the same characteristics as a first source follower circuit of a pixel. Accordingly, the second source follower circuit can generate a second reference voltage according to the change in characteristics of the first source follower circuit. A noise voltage switching circuit outputs a first voltage as a noise voltage to a pixel signal generator when the noise voltage is equal to or lower than the second reference voltage. In a reset state, the noise voltage and the second reference voltage always have a predetermined voltage difference. Therefore, deterioration in image quality can be prevented even when capturing a subject having high brightness. Since a trimming circuit or the like selecting any one of a plurality of reference voltages according to characteristics of a formed transistor becomes unnecessary, the cost of an imaging device can be reduced.
    Type: Grant
    Filed: May 20, 2005
    Date of Patent: January 13, 2009
    Assignee: Fujitsu Limited
    Inventors: Tsuyoshi Higuchi, Jun Funakoshi, Seiji Yamagata, Toshitaka Mizuguchi, Katsuyoshi Yamamoto
  • Publication number: 20080298716
    Abstract: A solid-state imaging device capable of correcting defective pixel signals to improve image quality. A line memory provides a value of a pixel currently selected for correction, together with values of its surrounding pixels. The surrounding pixels include corrected pixels preceding the selected pixel and uncorrected pixels succeeding the selected pixel. An extreme value remover removes effectively a maximum and minimum pixel values from the values of the corrected pixels read out of the line memory. An average calculator calculates an average value of the remaining uncorrected pixels and the corrected pixels read out of the line memory. A comparison processor compares the value of the selected pixel with the average value. If their difference exceeds a predetermined threshold, the comparison processor replaces the value of the selected pixel with the average value.
    Type: Application
    Filed: May 30, 2008
    Publication date: December 4, 2008
    Applicant: FUJITSU LIMITED
    Inventor: Seiji YAMAGATA
  • Patent number: 7460097
    Abstract: Lower level of data latch holding a digital image data and a positive selector arranged immediately above positive gradation voltage line, for selecting positive analog gradation voltage of positive gradation levels are take as a set, and upper level of data latch holding a digital image data and a negative selector arranged immediately above negative gradation voltage line, for selecting negative analog gradation voltage of negative gradation levels are take as a set. Two sets are arranged in alignment in vertical direction. A plurality of sets of vertically aligned sets are arranged horizontally to shorten a length in horizontal direction with respect to gradation voltage lines.
    Type: Grant
    Filed: September 1, 2004
    Date of Patent: December 2, 2008
    Assignee: Fujitsu Limited
    Inventors: Seiji Yamagata, Masatoshi Kokubun, Shinya Udo
  • Patent number: 7369170
    Abstract: A method for controlling a solid-state imaging apparatus, which includes a plurality of pixels, includes selecting a resetting element of one of the pixels, resetting a detecting unit connected to the pixel, transmitting to a detecting unit, an electric charge accumulated after photoelectric conversion performed by a photoelectric converting element of the pixel, and providing control to set a second end of a transmitting control signal line to an open state.
    Type: Grant
    Filed: November 30, 2004
    Date of Patent: May 6, 2008
    Assignee: Fujitsu Limited
    Inventors: Tsuyoshi Higuchi, Jun Funakoshi, Seiji Yamagata, Toshitaka Mizuguchi, Katsuyoshi Yamamoto
  • Patent number: 7218166
    Abstract: A circuit for stabilizing an electric current includes a constant voltage supplying circuit configured to supply a constant voltage, and a current generating circuit coupled to the constant voltage supplying circuit to generate an electric current based on a predetermined voltage responsive to the constant voltage and to adjust a current amount of the electric current to a predetermined amount by feedback control based on comparison of the predetermined voltage with a voltage appearing across a predetermined resistance responsive to the electric current.
    Type: Grant
    Filed: November 19, 2004
    Date of Patent: May 15, 2007
    Assignee: Fujitsu Limited
    Inventors: Makoto Yanagisawa, Jun Funakoshi, Seiji Yamagata, Toshitaka Mizuguchi, Tsuyoshi Higuchi
  • Patent number: 7145494
    Abstract: A differential comparator which outputs positive and/or negative logic signals to an output terminal according to the coincidence/non-coincidence of first and second input signal levels inputted to first and second input terminals, respectively, comprises an offset cancel function composed of an offset capacitor device provided on the differential comparator side of the first and second terminals, a first switch for short-circuiting the first and second input terminals in such a way as to form a closed loop including the offset capacitor device, and a second switch for short-circuiting both the connection point between the offset capacitor device and the differential comparator, and the output terminal.
    Type: Grant
    Filed: December 10, 2004
    Date of Patent: December 5, 2006
    Assignee: Fujitsu Limited
    Inventors: Toshitaka Mizuguchi, Jun Funakoshi, Seiji Yamagata, Tsuyoshi Higuchi
  • Publication number: 20060170794
    Abstract: A second source follower circuit of a reference voltage generator includes a transistor having the same characteristics as a first source follower circuit of a pixel. Accordingly, the second source follower circuit can generate a second reference voltage according to the change in characteristics of the first source follower circuit. A noise voltage switching circuit outputs a first voltage as a noise voltage to a pixel signal generator when the noise voltage is equal to or lower than the second reference voltage. In a reset state, the noise voltage and the second reference voltage always have a predetermined voltage difference. Therefore, deterioration in image quality can be prevented even when capturing a subject having high brightness. Since a trimming circuit or the like selecting any one of a plurality of reference voltages according to characteristics of a formed transistor becomes unnecessary, the cost of an imaging device can be reduced.
    Type: Application
    Filed: May 20, 2005
    Publication date: August 3, 2006
    Inventors: Tsuyoshi Higuchi, Jun Funakoshi, Seiji Yamagata, Toshitaka Mizuguchi, Katsuyoshi Yamamoto
  • Publication number: 20060170795
    Abstract: A differential amplifier has a first input terminal to which a voltage of a noise signal of the solid-state imaging device is supplied and a second input terminal to which a voltage of a temporary data signal having the noise signal of the solid-state imaging device superposed thereon is supplied. The differential amplifier inverts an output signal when a magnitude relationship in voltage between the first and second input terminals becomes reverse. A measurement circuit measures a variation amount of a voltage of the second input terminal from when the voltage of the second input terminal begins to vary in a direction to reverse the magnitude relationship to when the output signal of the differential amplifier is inverted, and outputs a measurement result as a digital value indicating a voltage of a real data signal obtained by removing the noise signal from the temporary data signal.
    Type: Application
    Filed: May 27, 2005
    Publication date: August 3, 2006
    Inventors: Tsuyoshi Higuchi, Jun Funakoshi, Seiji Yamagata, Toshitaka Mizuguchi, Katsuyoshi Yamamoto
  • Patent number: 7075474
    Abstract: A ramp waveform generation circuit which comprises a first reference power supply, and supplies a ramp waveform signal to an analog/digital conversion circuit further comprises a connection circuit for reflecting the amount of fluctuation of the output potential of a second reference power supply which is installed in a noise elimination circuit for eliminating the noise of an analog signal inputted to the analog/digital conversion circuit in the output potential of the first reference power supply.
    Type: Grant
    Filed: November 30, 2004
    Date of Patent: July 11, 2006
    Assignee: Fujitsu Limited
    Inventors: Seiji Yamagata, Jun Funakoshi, Tsuyoshi Higuchi, Toshitaka Mizuguchi
  • Publication number: 20060001564
    Abstract: A ramp waveform generation circuit which comprises a first reference power supply, and supplies a ramp waveform signal to an analog/digital conversion circuit further comprises a connection circuit for reflecting the amount of fluctuation of the output potential of a second reference power supply which is installed in a noise elimination circuit for eliminating the noise of an analog signal inputted to the analog/digital conversion circuit in the output potential of the first reference power supply.
    Type: Application
    Filed: November 30, 2004
    Publication date: January 5, 2006
    Inventors: Seiji Yamagata, Jun Funakoshi, Tsuyoshi Higuchi, Toshitaka Mizuguchi
  • Publication number: 20060001750
    Abstract: A differential comparator which outputs positive and/or negative logic signals to an output terminal according to the coincidence/non-coincidence of first and second input signal levels inputted to first and second input terminals, respectively, comprises an offset cancel function composed of an offset capacitor device provided on the differential comparator side of the first and second terminals, a first switch for short-circuiting the first and second input terminals in such a way as to form a closed loop including the offset capacitor device, and a second switch for short-circuiting both the connection point between the offset capacitor device and the differential comparator, and the output terminal.
    Type: Application
    Filed: December 10, 2004
    Publication date: January 5, 2006
    Inventors: Toshitaka Mizuguchi, Jun Funakoshi, Seiji Yamagata, Tsuyoshi Higuchi
  • Publication number: 20060001476
    Abstract: A circuit for stabilizing an electric current includes a constant voltage supplying circuit configured to supply a constant voltage, and a current generating circuit coupled to the constant voltage supplying circuit to generate an electric current based on a predetermined voltage responsive to the constant voltage and to adjust a current amount of the electric current to a predetermined amount by feedback control based on comparison of the predetermined voltage with a voltage appearing across a predetermined resistance responsive to the electric current.
    Type: Application
    Filed: November 19, 2004
    Publication date: January 5, 2006
    Inventors: Makoto Yanagisawa, Jun Funakoshi, Seiji Yamagata, Toshitaka Mizuguchi, Tsuyoshi Higuchi
  • Publication number: 20060001749
    Abstract: A method for controlling a solid-state imaging apparatus, which includes a plurality of pixels, includes selecting a resetting element of one of the pixels, resetting a detecting unit connected to the pixel, transmitting to a detecting unit, an electric charge accumulated after photoelectric conversion performed by a photoelectric converting element of the pixel, and providing control to set a second end of a transmitting control signal line to an open state.
    Type: Application
    Filed: November 30, 2004
    Publication date: January 5, 2006
    Inventors: Tsuyoshi Higuchi, Jun Funakoshi, Seiji Yamagata, Toshitaka Mizuguchi, Katsuyoshi Yamamoto
  • Patent number: 6864873
    Abstract: Lower level of data latch holding a digital image data and a positive selector arranged immediately above positive gradation voltage line, for selecting positive analog gradation voltage of positive gradation levels are take as a set, and upper level of data latch holding a digital image data and a negative selector arranged immediately above negative gradation voltage line, for selecting negative analog gradation voltage of negative gradation levels are take as a set. Two sets are arranged in alignment in vertical direction. A plurality of sets of vertically aligned sets are arranged horizontally to shorten a length in horizontal direction with respect to gradation voltage lines.
    Type: Grant
    Filed: December 11, 2000
    Date of Patent: March 8, 2005
    Assignee: Fujitsu Limited
    Inventors: Seiji Yamagata, Masatoshi Kokubun, Shinya Udo
  • Publication number: 20050024315
    Abstract: Lower level of data latch holding a digital image data and a positive selector arranged immediately above positive gradation voltage line, for selecting positive analog gradation voltage of positive gradation levels are take as a set, and upper level of data latch holding a digital image data and a negative selector arranged immediately above negative gradation voltage line, for selecting negative analog gradation voltage of negative gradation levels are take as a set. Two sets are arranged in alignment in vertical direction. A plurality of sets of vertically aligned sets are arranged horizontally to shorten a length in horizontal direction with respect to gradation voltage lines.
    Type: Application
    Filed: September 1, 2004
    Publication date: February 3, 2005
    Applicant: Fujitsu Limited
    Inventors: Seiji Yamagata, Masatoshi Kokubun, Shinya Udo
  • Patent number: 6448836
    Abstract: An offset cancel circuit for an operational amplifier comprises a capacitive element for storing a voltage to be amplified by an operational amplifier section and containing an offset, and for feedback-controlling a voltage value of the operational amplifier section based on the stored voltage, and switching elements for switching operation between the storage of the voltage in the capacitive element and the feedback control based on the value of the voltage stored in the capacitive element. The capacitive element and the switching elements can be used to cancel accurately an offset in the operational amplifier section without increasing the gate areas of transistors in the operational amplifier section.
    Type: Grant
    Filed: December 8, 2000
    Date of Patent: September 10, 2002
    Assignee: Fujitsu Limited
    Inventors: Masatoshi Kokubun, Shinya Udo, Seiji Yamagata, Chikara Tsuchiya
  • Publication number: 20020008562
    Abstract: An offset cancel circuit for an operational amplifier comprises a capacitive element for storing a voltage to be amplified by an operational amplifier section and containing an offset, and for feedback-controlling a voltage value of the operational amplifier section based on the stored voltage, and switching elements for switching operation between the storage of the voltage in the capacitive element and the feedback control based on the value of the voltage stored in the capacitive element. The capacitive element and the switching elements can be used to cancel accurately an offset in the operational amplifier section without increasing the gate areas of transistors in the operational amplifier section.
    Type: Application
    Filed: December 8, 2000
    Publication date: January 24, 2002
    Applicant: FUJITSU LIMITED
    Inventors: Masatoshi Kokubun, Shinya Udo, Seiji Yamagata, Chikara Tsuchiya
  • Patent number: 6304241
    Abstract: A liquid crystal display panel includes a driver having pairs of first and second D/A converters, corresponding pairs of first and second polarity changeover switches, and plural switching elements. Each of the first D/A converters receives a picture signal and outputs a positive-polarity voltage and each of the second D/A converters receives the picture signal and outputs a negative-polarity voltage. The first polarity changeover switches are connected to the outputs of the first and second D/A converters and alternately output the positive and negative polarity voltages. The second polarity changeover switches are also connected to the outputs of the first and second D/A converters and output a reverse polarity voltages. The switching elements are connected between the outputs of the first D/A converters and the first polarity switch and the output of the second D/A converters and the second polarity changeover switch.
    Type: Grant
    Filed: December 7, 1998
    Date of Patent: October 16, 2001
    Assignee: Fujitsu Limited
    Inventors: Shinya Udo, Seiji Yamagata, Masatoshi Kokubun